A highly manufacturable deep trench based DRAM cell layout with a planar array device in a 70nm technology

Technical Digest - International Electron Devices Meeting, IEDM

Volumn , Issue , 2004, Pages 73-74

  Amon, J ^a   Kieslich, A ^a   Heineck, L ^a   Schuster, T ^a   Faul, J ^a   Luetzen, J ^a   Fan, C ^a   Huang, C C ^a   Fischer, B ^a   Enders, G ^a   Kudelka, S ^a   Schroeder, U ^a   Kuesters, K H ^a   Lange, G ^a   Alsmeier, J ^a  

^a INFINEON TECHNOLOGIES AG   (Germany)

Author keywords

[No Author keywords available]

Indexed keywords

CHECKERBOARD (CKB); DEEP TRENCH (DT) TECHNOLOGY; HEMISPHERICAL SILICON GRAINS (HSG); ISOLATION TRENCH (IT); ARRAY DEVICES; CELL LAYOUT; DEEP TRENCH; DEEP TRENCH TECHNOLOGIES; DRAM CELLS; ETCH PROCESS; HIGH ASPECT RATIO; INTEGRATION SCHEME; PLANAR ARRAYS; SELF-ALIGNED;

ALUMINA; AMORPHOUS SILICON; ANISOTROPY; ASPECT RATIO; CAPACITORS; DIELECTRIC MATERIALS; ETCHING; GATES (TRANSISTOR); LITHOGRAPHY; PARALLEL PROCESSING SYSTEMS; SEMICONDUCTOR DEVICE MANUFACTURE; SEMICONDUCTOR DOPING; TRENCHING; HIGH-K DIELECTRIC; INTEGRATED CIRCUIT LAYOUT;

DYNAMIC RANDOM ACCESS STORAGE; ALUMINUM OXIDE;

EID: 21644481387     PISSN: 01631918     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (6)

1. U. Gruening et al., A novel trench DRAM Cell with a VERtlcal Access Transistor and BuriEd Strap (VERI BEST) for 4Gb/16Gb, IEDM Tech. Dig, pp. 25-28, 1999.
2. R. Divakaruni et al., Technologies for Vertical Transistor DRAM Cells to 70nm, Symp. on VLSI Tech., pp. 59-60, 2003.
3. J.Y. Kim et al., The Breakthrough in data retention time of DRAM using Recess-Channel-Array Transistor (RCAT) for 88nm feature size and beyond, Symp. on VLSI Tech., pp. 11-12, 2003.
4. H.S. Kim et al., An outstanding and highly manufacturable 80nm DRAM Technology, IEDM Tech. Dig, pp. 17.2.1-4, 2003.
5. L. Nesbit et al., 1993 IEDM Techn. Dig., pp. 627-630, 1993.
6. K.H. Kuesters et al., Semiconductor Fabtech, 19th edition, pp 97-101, 2003.