Low-voltage limitations of memory-rich nano-scale CMOS LSIs

ESSCIRC 2007 - Proceedings of the 33rd European Solid-State Circuits Conference

Volumn , Issue , 2007, Pages 68-75

  Itoh, Kiyoo ^a   Horiguchi, Masashi ^b   Yamaoka, Masanao ^a  

^a HITACHI LTD   (Japan)

^b RENESAS TECHNOLOGY CORP   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; ELECTRIC POTENTIAL; LSI CIRCUITS; NANOTECHNOLOGY;

BULK CMOS; CMOS INVERTERS; EUROPEAN; FULLY-DEPLETED (FD); LOW-VOLTAGE (LV); NANO-SCALE CMOS; SENSE AMPLIFIER (SA); SILICON ON INSULATOR (SOI) DEVICES; SOLID-STATE CIRCUITS CONFERENCE;

NANOSTRUCTURED MATERIALS;

EID: 44849138475     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ESSCIRC.2007.4430250     Document Type: Conference Paper

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