Tri-gate transistor architecture with high-k gate dielectrics, metal gates and strain engineering

Digest of Technical Papers - Symposium on VLSI Technology

Volumn , Issue , 2006, Pages 50-51

  Kavalieros, Jack ^a   Doyle, Brian ^a   Datta, Suman ^a   Dewey, Gilbert ^a   Doczy, Mark ^a   Jin, Ben ^a   Lionberger, Dan ^a   Metz, Matthew ^a   Rachmady, Willy ^a   Radosavljevic, Marko ^a   Shah, Uday ^a   Zelick, Nancy ^a   Chau, Robert ^a  

^a INTEL CORPORATION   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

DOPING (ADDITIVES); GATE DIELECTRICS; STRAIN; THRESHOLD VOLTAGE;

STRAIN ENGINEERING; SUBSTRATE ORIENTATIONS;

TRANSISTORS;

EID: 41149171855     PISSN: 07431562     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (8)

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