A self-tuning DVS processor using delay-error detection and correction

IEEE Journal of Solid-State Circuits

Volumn 41, Issue 4, 2006, Pages 792-803

  Das, Shidhartha ^a,b   Roberts, David ^a,b,d   Lee, Seokwoo ^b   Pant, Sanjay ^b   Blaauw, David ^a,b   Austin, Todd ^b,e   Flautner, Krisztián ^a,c,e   Mudge, Trevor ^a,b,d,e,f  

^a IEEE   (United States)

^b UNIVERSITY OF MICHIGAN   (United States)

^c ARM LTD   (United Kingdom)

^d British Computer Society ^*  (United Kingdom)

^e ASSOCIATION FOR COMPUTING MACHINERY   (United States)

^f Institution of Electrical Engineers IEE   (United Kingdom)

Author keywords

Dynamic voltage scaling (DVS); Error detection and correction; Self tuning processor; Voltage safety margins

Indexed keywords

DYNAMIC VOLTAGE SCALING (DVS); ERROR DETECTION AND CORRECTION; SELF-TUNING PROCESSOR; VOLTAGE SAFETY MARGINS;

ENERGY DISSIPATION; ENERGY EFFICIENCY; ERROR DETECTION; FAILURE ANALYSIS; SOLID STATE DEVICES; VOLTAGE CONTROL;

VOLTAGE MEASUREMENT;

EID: 33645652998     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/JSSC.2006.870912     Document Type: Conference Paper

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