-
1
-
-
21644445541
-
-
2) 6T-SRAM cell for the 32 nm node and beyond, in Int. Electron Devices Meeting Tech, Dig., Dec. 2004, pp. 261-264.
-
2) 6T-SRAM cell for the 32 nm node and beyond," in Int. Electron Devices Meeting Tech, Dig., Dec. 2004, pp. 261-264.
-
-
-
-
2
-
-
33846284604
-
Characteristics and modeling of sub-10-nm planar bulk CMOS devices fabricated by lateral source/drain junction control
-
Sep
-
H. Wakabayashi, T. Ezaki, T. Sakamoto, H. Kawaura, N. Ikarashi, N. Ikezawa, M. Narihiro, Y. Ochiai, T. Ikezawa, K. Takeuchi, T. Yamamoto, M. Hane, and T. Mogami, "Characteristics and modeling of sub-10-nm planar bulk CMOS devices fabricated by lateral source/drain junction control," IEEE Trans. Electron Devices, vol. 53, no. 9, pp. 715-720, Sep. 2006.
-
(2006)
IEEE Trans. Electron Devices
, vol.53
, Issue.9
, pp. 715-720
-
-
Wakabayashi, H.1
Ezaki, T.2
Sakamoto, T.3
Kawaura, H.4
Ikarashi, N.5
Ikezawa, N.6
Narihiro, M.7
Ochiai, Y.8
Ikezawa, T.9
Takeuchi, K.10
Yamamoto, T.11
Hane, M.12
Mogami, T.13
-
3
-
-
0036923554
-
Extreme scaling with ultra-thin Si channel MOSFETs
-
Dec
-
B. Doris, M. Ieong, T. Kanarsky, Y. Zhang, R. A. Roy, O. Dokumaci, Z. Ren, F. Jamin, L. Shi, W. Natzle, H.-J. Huang, J. Mezzapelle, A. Mocuta, S. Womack, M. Gribelyuk, E. C. Jones, R. J. Miller, H.-S. P. Wong, and W. Haensch, "Extreme scaling with ultra-thin Si channel MOSFETs," in Int. Electron Devices Meeting Tech. Dig., Dec. 2002, pp. 267-270.
-
(2002)
Int. Electron Devices Meeting Tech. Dig
, pp. 267-270
-
-
Doris, B.1
Ieong, M.2
Kanarsky, T.3
Zhang, Y.4
Roy, R.A.5
Dokumaci, O.6
Ren, Z.7
Jamin, F.8
Shi, L.9
Natzle, W.10
Huang, H.-J.11
Mezzapelle, J.12
Mocuta, A.13
Womack, S.14
Gribelyuk, M.15
Jones, E.C.16
Miller, R.J.17
Wong, H.-S.P.18
Haensch, W.19
-
4
-
-
36849066110
-
Sub-5 nm all-around gate FinFET for ultimate scaling
-
H. Lee, L.-E. Yu, S.-W. Ryu, J.-W. Han, K. Jeon, D.-Y. Jang, K.-H. Kim, J. Lee, J.-H. Kim, S. C. Jeon, G. S. Lee, J. S. Oh, Y. C. Park, W. H. Bae, H. M. Lee, J. M. Yang, J. J. Yoo, S. I. Kim, and Y.-K. Choi, "Sub-5 nm all-around gate FinFET for ultimate scaling," in VLSI Technol. Tech. Symp. Dig., 2006, pp. 58-59.
-
(2006)
VLSI Technol. Tech. Symp. Dig
, pp. 58-59
-
-
Lee, H.1
Yu, L.-E.2
Ryu, S.-W.3
Han, J.-W.4
Jeon, K.5
Jang, D.-Y.6
Kim, K.-H.7
Lee, J.8
Kim, J.-H.9
Jeon, S.C.10
Lee, G.S.11
Oh, J.S.12
Park, Y.C.13
Bae, W.H.14
Lee, H.M.15
Yang, J.M.16
Yoo, J.J.17
Kim, S.I.18
Choi, Y.-K.19
-
5
-
-
4544367603
-
5 nm-gate nanowire FinFET
-
Jun
-
F.-L. Yang, D.-H. Lee, H.-Y. Chen, C.-Y. Chang, S.-D. Liu, C.-C. Huang, T.-X. Chung, H.-W. Chen, C.-C. Huang, Y.-H. Liu, C.-C. Wu, C.-C. Chen, S.-C. Chen, Y.-T. Chen, Y.-H. Chen, C.-J. Chen, B.-W. Chan, P.-F. Hsu, J.-H. Shieh, H.-J. Tao, Y.-C. Yeo, Y. Li, J.-W. Lee, P. Chen, M.-S. Liang, and C. Hu, "5 nm-gate nanowire FinFET," in VLSI Technol. Tech. Symp. Dig., Jun. 2004, pp. 196-197.
-
(2004)
VLSI Technol. Tech. Symp. Dig
, pp. 196-197
-
-
Yang, F.-L.1
Lee, D.-H.2
Chen, H.-Y.3
Chang, C.-Y.4
Liu, S.-D.5
Huang, C.-C.6
Chung, T.-X.7
Chen, H.-W.8
Huang, C.-C.9
Liu, Y.-H.10
Wu, C.-C.11
Chen, C.-C.12
Chen, S.-C.13
Chen, Y.-T.14
Chen, Y.-H.15
Chen, C.-J.16
Chan, B.-W.17
Hsu, P.-F.18
Shieh, J.-H.19
Tao, H.-J.20
Yeo, Y.-C.21
Li, Y.22
Lee, J.-W.23
Chen, P.24
Liang, M.-S.25
Hu, C.26
more..
-
6
-
-
33847700489
-
High performance, sub-50 nm MOSFETs for mixed signal applications
-
Dec
-
V. Dimitrov, J. B. Heng, K. Timp, O. Dimauro, R. Chan, J. Feng, W. Hafez, T. Sorsch, W. Mansfield, J. Miner, A. Kornblit, F. Klemens, J. Bower, R. Cirelli, E. Ferry, A. Taylor, M. Feng, and G. Timp. "High performance, sub-50 nm MOSFETs for mixed signal applications," in Int. Electron Devices Meeting Tech. Dig., Dec. 2005, pp. 213-216.
-
(2005)
Int. Electron Devices Meeting Tech. Dig
, pp. 213-216
-
-
Dimitrov, V.1
Heng, J.B.2
Timp, K.3
Dimauro, O.4
Chan, R.5
Feng, J.6
Hafez, W.7
Sorsch, T.8
Mansfield, W.9
Miner, J.10
Kornblit, A.11
Klemens, F.12
Bower, J.13
Cirelli, R.14
Ferry, E.15
Taylor, A.16
Feng, M.17
Timp, G.18
-
7
-
-
46049083438
-
A 65 nm CMOS SOC technology featuring strained silicon transistors for RF applications
-
Dec
-
I. Post, M. Akbar, G. Curello, S. Gannavaram, W. Hafez, U. Jalan, K. Komeyii, J. Lin, N. Lindert, J. Park, J. Rizk, G. Sacks, C. Tsai, D. Yeh, P. Bai, and C.-H. Jan, "A 65 nm CMOS SOC technology featuring strained silicon transistors for RF applications," in Int. Electron Devices Meeting Tech. Dig., Dec. 2006, pp. 1-3.
-
(2006)
Int. Electron Devices Meeting Tech. Dig
, pp. 1-3
-
-
Post, I.1
Akbar, M.2
Curello, G.3
Gannavaram, S.4
Hafez, W.5
Jalan, U.6
Komeyii, K.7
Lin, J.8
Lindert, N.9
Park, J.10
Rizk, J.11
Sacks, G.12
Tsai, C.13
Yeh, D.14
Bai, P.15
Jan, C.-H.16
-
8
-
-
0026888165
-
Integrated physics-oriented statistical modeling, simulation and optimization
-
Jul
-
J. W. Bandler, R. M. Biemacki, Q. Cai, S. H. Chen, S. Ye, and Q. J. Zhang, "Integrated physics-oriented statistical modeling, simulation and optimization," IEEE Trans. Microw. Theory Tech., vol. 40, no. 7, pp. 1374-1400, Jul. 1992.
-
(1992)
IEEE Trans. Microw. Theory Tech
, vol.40
, Issue.7
, pp. 1374-1400
-
-
Bandler, J.W.1
Biemacki, R.M.2
Cai, Q.3
Chen, S.H.4
Ye, S.5
Zhang, Q.J.6
-
9
-
-
0026888366
-
Yield optimization using a GaAs process simulator coupled to a physical device model
-
Jul
-
D. E. Stoneking, G. L. Bilbro, P. A. Gilmore, R. J. Trew, and C. T. Kelley, "Yield optimization using a GaAs process simulator coupled to a physical device model," IEEE Trans. Microw. Theory Tech., vol. 40, no. 7, pp. 1353-1363, Jul. 1992.
-
(1992)
IEEE Trans. Microw. Theory Tech
, vol.40
, Issue.7
, pp. 1353-1363
-
-
Stoneking, D.E.1
Bilbro, G.L.2
Gilmore, P.A.3
Trew, R.J.4
Kelley, C.T.5
-
10
-
-
0029322064
-
A neural network modeling approach to circuit optimization and statistical design
-
Jun
-
A. H. Zaabab, Q.-J. Zhang, and M. Nakhla, "A neural network modeling approach to circuit optimization and statistical design," IEEE Trans. Microw. Theory Tech., vol. 43, no. 6, pp. 1349-1358, Jun. 1995.
-
(1995)
IEEE Trans. Microw. Theory Tech
, vol.43
, Issue.6
, pp. 1349-1358
-
-
Zaabab, A.H.1
Zhang, Q.-J.2
Nakhla, M.3
-
11
-
-
0025717410
-
CAD for statistical analysis and design of microwave circuits
-
Jan
-
J. Purviance and M. Meehan, "CAD for statistical analysis and design of microwave circuits," Int. J. Microw. Millimeter-Wave Comput.-Aided Eng., vol. I, no. 1, pp. 59-76, Jan. 1991.
-
(1991)
Int. J. Microw. Millimeter-Wave Comput.-Aided Eng
, vol.1
, Issue.1
, pp. 59-76
-
-
Purviance, J.1
Meehan, M.2
-
12
-
-
0035444824
-
RF circuit performance degradation due to soft breakdown and hot-carrier effect in deep-submicrometer CMOS technology
-
Sep
-
Q. Li, J. Zhang, Li Wei, J. S. Yuan, Y. Chen, and A. S. Oates, "RF circuit performance degradation due to soft breakdown and hot-carrier effect in deep-submicrometer CMOS technology," IEEE Trans. Microw. Theory Tech., vol. 49, no. 9, pp. 1546-1551, Sep. 2001.
-
(2001)
IEEE Trans. Microw. Theory Tech
, vol.49
, Issue.9
, pp. 1546-1551
-
-
Li, Q.1
Zhang, J.2
Wei, L.3
Yuan, J.S.4
Chen, Y.5
Oates, A.S.6
-
13
-
-
54549115996
-
Large-scale atomistic approach to discrete-dopant-induced characteristic fluctuations in silicon nanowire transistors
-
May
-
Y. Li, C.-H. Hwang, and H.-M. Huang, "Large-scale atomistic approach to discrete-dopant-induced characteristic fluctuations in silicon nanowire transistors," Phys. Status Solidi (a), vol. 205, no. 6, pp. 1505-1510, May 2008.
-
(2008)
Phys. Status Solidi (a)
, vol.205
, Issue.6
, pp. 1505-1510
-
-
Li, Y.1
Hwang, C.-H.2
Huang, H.-M.3
-
14
-
-
0032157146
-
Discrete random dopant distribution effects in nanometer-scale MOSFETs
-
Sep
-
H.-S. Wong, Y. Taur, and D. J. Frank, "Discrete random dopant distribution effects in nanometer-scale MOSFETs," Microelectron. Rel., vol. 38, no. 9, pp. 1447-1456, Sep. 1999.
-
(1999)
Microelectron. Rel
, vol.38
, Issue.9
, pp. 1447-1456
-
-
Wong, H.-S.1
Taur, Y.2
Frank, D.J.3
-
15
-
-
0016572578
-
Effect of randomness in distribution of impurity atoms on FET thresholds
-
R. W. Keyes, "Effect of randomness in distribution of impurity atoms on FET thresholds," Appl. Phys., vol. 8, pp. 251-259, 1975.
-
(1975)
Appl. Phys
, vol.8
, pp. 251-259
-
-
Keyes, R.W.1
-
16
-
-
0028427763
-
Modeling of ultrathin doublegate NMOS/SOI transistors
-
May
-
P. Francis, A. Terao, and D. Flandre, "Modeling of ultrathin doublegate NMOS/SOI transistors," IEEE Trans. Electron Device, vol. 41, no. 5, pp. 715-720, May 1994.
-
(1994)
IEEE Trans. Electron Device
, vol.41
, Issue.5
, pp. 715-720
-
-
Francis, P.1
Terao, A.2
Flandre, D.3
-
17
-
-
0031365880
-
Intrinsic MOSFET parameter fluctuations due to random dopant placement
-
Dec
-
X.-H. Tang, V. K. De, and J. D. Meindl, "Intrinsic MOSFET parameter fluctuations due to random dopant placement," IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 5, no. 4, pp. 369-376, Dec. 1997.
-
(1997)
IEEE Trans. Very Large Scale Integr. (VLSI) Syst
, vol.5
, Issue.4
, pp. 369-376
-
-
Tang, X.-H.1
De, V.K.2
Meindl, J.D.3
-
18
-
-
0032164821
-
Modeling statistical dopant fluctuations in MOS transistors
-
Sep
-
P. A. Stolk, F. P. Widdershoven, and D. B. M. Klaassen, "Modeling statistical dopant fluctuations in MOS transistors," IEEE Trans. Electron Device, vol. 45, no. 9, pp. 1960-1971, Sep. 1998.
-
(1998)
IEEE Trans. Electron Device
, vol.45
, Issue.9
, pp. 1960-1971
-
-
Stolk, P.A.1
Widdershoven, F.P.2
Klaassen, D.B.M.3
-
19
-
-
33749022999
-
Comparison of random-dopant-induced threshold voltage fluctuation in nanoscale single-, double-, and surrounding-gate field-effect transistors
-
Sep
-
Y. Li and S.-M. Yu, "Comparison of random-dopant-induced threshold voltage fluctuation in nanoscale single-, double-, and surrounding-gate field-effect transistors," Jpn. J. Appl. Phys., vol. 45, no. 9A, pp. 6860-6865, Sep. 2006.
-
(2006)
Jpn. J. Appl. Phys
, vol.45
, Issue.9 A
, pp. 6860-6865
-
-
Li, Y.1
Yu, S.-M.2
-
20
-
-
44949159936
-
Discrete dopant fluctuated 20 nm/15 nm-gate planar CMOS
-
Jun
-
Y. Li, S.-M. Yu, J.-R. Hwang, and F.-L. Yang, "Discrete dopant fluctuated 20 nm/15 nm-gate planar CMOS," IEEE Trans. Electron Device, vol. 55, no. 6, pp. 1449-1455, Jun. 2008.
-
(2008)
IEEE Trans. Electron Device
, vol.55
, Issue.6
, pp. 1449-1455
-
-
Li, Y.1
Yu, S.-M.2
Hwang, J.-R.3
Yang, F.-L.4
-
21
-
-
34548282704
-
Electrical characteristic fluctuations in sub-45 nm CMOS devices
-
Sep
-
F.-L. Yang, J.-R. Hwang, and Y. Li, "Electrical characteristic fluctuations in sub-45 nm CMOS devices," in IEEE Custom Integr. Circuits Conf., Sep. 2006, pp. 691-694.
-
(2006)
IEEE Custom Integr. Circuits Conf
, pp. 691-694
-
-
Yang, F.-L.1
Hwang, J.-R.2
Li, Y.3
-
22
-
-
34248644874
-
Process-variation- and random-dopants-induced threshold voltage fluctuations in nanoscale CMOS and SOI devices
-
Sep.-Oct
-
Y. Li, S.-M. Yu, and H.-M. Chen, "Process-variation- and random-dopants-induced threshold voltage fluctuations in nanoscale CMOS and SOI devices," Microelectron. Eng., vol. 84, no. 9-10, pp. 2117-2120, Sep.-Oct. 2007.
-
(2007)
Microelectron. Eng
, vol.84
, Issue.9-10
, pp. 2117-2120
-
-
Li, Y.1
Yu, S.-M.2
Chen, H.-M.3
-
23
-
-
52649096841
-
Discrete-dopant-induced characteristic fluctuations in 16 nm multiple-gate silicon-on-insulator devices
-
Y. Li and C.-H. Hwang, "Discrete-dopant-induced characteristic fluctuations in 16 nm multiple-gate silicon-on-insulator devices," J. Appl. Phy., vol. 102, no. 8, pp. 084509-084509, 2007.
-
(2007)
J. Appl. Phy
, vol.102
, Issue.8
, pp. 084509-084509
-
-
Li, Y.1
Hwang, C.-H.2
-
24
-
-
52649130153
-
A coupled-simulation-and-optimization approach to nanodevice fabrication with minimization of electrical characteristics fluctuation
-
Nov
-
Y. Li and S.-M. Yu, "A coupled-simulation-and-optimization approach to nanodevice fabrication with minimization of electrical characteristics fluctuation," IEEE Trans. Semicond. Manuf., vol. 20, no. 4, pp. 432-438, Nov. 2007.
-
(2007)
IEEE Trans. Semicond. Manuf
, vol.20
, Issue.4
, pp. 432-438
-
-
Li, Y.1
Yu, S.-M.2
-
25
-
-
34248662830
-
A study of threshold voltage fluctuations of nanoscale double gate metal-oxide-semiconductor field effect transistors using quantum correction simulation
-
Jul
-
Y. Li and S.-M. Yu, "A study of threshold voltage fluctuations of nanoscale double gate metal-oxide-semiconductor field effect transistors using quantum correction simulation," J. Comput. Electron., vol. 5, no. 2-3, pp. 125-129, Jul. 2006.
-
(2006)
J. Comput. Electron
, vol.5
, Issue.2-3
, pp. 125-129
-
-
Li, Y.1
Yu, S.-M.2
-
26
-
-
0041537563
-
Intrinsic fluctuations in sub 10-nm double-gate MOSFETs introduced by discreteness of charge and matter
-
Dec
-
A. R. Brown, A. Asenov, and J. R. Watling, "Intrinsic fluctuations in sub 10-nm double-gate MOSFETs introduced by discreteness of charge and matter," IEEE Trans. Nanotechnol., vol. 1, no. 4, pp. 195-200, Dec. 2002.
-
(2002)
IEEE Trans. Nanotechnol
, vol.1
, Issue.4
, pp. 195-200
-
-
Brown, A.R.1
Asenov, A.2
Watling, J.R.3
-
27
-
-
0033169519
-
Suppression of random dopant-induced threshold voltage fluctuations in sub-0.1-μm MOSFET's with epitaxial and doped channels
-
Aug
-
A. Asenov and S. Saini, "Suppression of random dopant-induced threshold voltage fluctuations in sub-0.1-μm MOSFET's with epitaxial and doped channels," IEEE Trans. Electron Devices, vol. 46, no. 8, pp. 1718-1724, Aug. 1999.
-
(1999)
IEEE Trans. Electron Devices
, vol.46
, Issue.8
, pp. 1718-1724
-
-
Asenov, A.1
Saini, S.2
-
28
-
-
0000115765
-
A 0.1-m delta doped MOSFET fabricated with post-low-energy implanting selective epitaxy
-
Apr
-
K. Noda, T. Tatsumi, T. Uchida, K. Nakajima, H. Miyamoto, and C. Hu, "A 0.1-m delta doped MOSFET fabricated with post-low-energy implanting selective epitaxy," IEEE Trans. Electron Devices, vol. 45, no. 4, pp. 809-813, Apr. 1998.
-
(1998)
IEEE Trans. Electron Devices
, vol.45
, Issue.4
, pp. 809-813
-
-
Noda, K.1
Tatsumi, T.2
Uchida, T.3
Nakajima, K.4
Miyamoto, H.5
Hu, C.6
-
29
-
-
84886448051
-
Channel engineering for the reduction of random-dopant-placement-induced threshold voltage fluctuations
-
Dec
-
K. Takeuchi, T. Tatsumi, and A. Furukawa, "Channel engineering for the reduction of random-dopant-placement-induced threshold voltage fluctuations," in Int. Electron Devices Meeting Tech. Dig., Dec. 1997. pp. 841-844.
-
(1997)
Int. Electron Devices Meeting Tech. Dig
, pp. 841-844
-
-
Takeuchi, K.1
Tatsumi, T.2
Furukawa, A.3
-
30
-
-
33947265310
-
Simulation study of individual and combined sources of intrinsic parameter fluctuations in conventional nano-MOSFETs
-
Dec
-
G. Roy, A. R. Brown, F. Adamu-Lema, S. Roy, and A. Asenov, "Simulation study of individual and combined sources of intrinsic parameter fluctuations in conventional nano-MOSFETs," IEEE Trans. Electron Devices, vol. 53, no. 12, pp. 3063-3070, Dec. 2006.
-
(2006)
IEEE Trans. Electron Devices
, vol.53
, Issue.12
, pp. 3063-3070
-
-
Roy, G.1
Brown, A.R.2
Adamu-Lema, F.3
Roy, S.4
Asenov, A.5
-
31
-
-
0032595866
-
A novel approach for introducing the electron-electron and electron-impurity interactions in particle-based simulations
-
Sep
-
W. J. Gross, D. Vasileska, and D. K. Ferry, "A novel approach for introducing the electron-electron and electron-impurity interactions in particle-based simulations," IEEE Electron Device Lett., vol. 20, no. 9, pp. 463-465, Sep. 1999.
-
(1999)
IEEE Electron Device Lett
, vol.20
, Issue.9
, pp. 463-465
-
-
Gross, W.J.1
Vasileska, D.2
Ferry, D.K.3
-
32
-
-
42549130489
-
Investigation of snm with random dopant fluctuations for FD SGSOI and FinFET 6T SOI SRAM cell by three-dimensional device simulation
-
Sep
-
R. Tanabe, Y. Ashizawa, and H. Oka, "Investigation of snm with random dopant fluctuations for FD SGSOI and FinFET 6T SOI SRAM cell by three-dimensional device simulation," in Simulation Semicond. Processes Device Conf., Sep. 2006, pp. 103-106.
-
(2006)
Simulation Semicond. Processes Device Conf
, pp. 103-106
-
-
Tanabe, R.1
Ashizawa, Y.2
Oka, H.3
-
33
-
-
34547307410
-
Impact of intrinsic parameter fluctuations on SRAM cell design
-
Oct
-
B. Cheng, S. Roy, G. Roy, and A. Asenov, "Impact of intrinsic parameter fluctuations on SRAM cell design," in Int. Solid-State Integr. Circuit Technol. Conf., Oct. 2006, pp. 1290-1292.
-
(2006)
Int. Solid-State Integr. Circuit Technol. Conf
, pp. 1290-1292
-
-
Cheng, B.1
Roy, S.2
Roy, G.3
Asenov, A.4
-
34
-
-
25144443976
-
Estimation of delay variations due to random-dopant fluctuations in nanoscale CMOS circuits
-
Sep
-
H. Mahmoodi, S. Mukhopadhyay, and K. Roy, "Estimation of delay variations due to random-dopant fluctuations in nanoscale CMOS circuits," IEEE J. Solid-State Circuits, vol. 40, no. 9, pp. 1787-1796, Sep. 2005.
-
(2005)
IEEE J. Solid-State Circuits
, vol.40
, Issue.9
, pp. 1787-1796
-
-
Mahmoodi, H.1
Mukhopadhyay, S.2
Roy, K.3
-
35
-
-
84943197898
-
Impact of random dopant fluctuation on bulk CMOS 6-T SRAM scaling
-
Sep
-
B. Cheng, S. Roy, G. Roy, A. Brown, and A. Asenov, "Impact of random dopant fluctuation on bulk CMOS 6-T SRAM scaling," in Proc. 36th Eur. Solid-State Device Res. Conf., Sep. 2006, pp. 258-261.
-
(2006)
Proc. 36th Eur. Solid-State Device Res. Conf
, pp. 258-261
-
-
Cheng, B.1
Roy, S.2
Roy, G.3
Brown, A.4
Asenov, A.5
-
37
-
-
0000776042
-
Macroscopic physics of the silicon inversion layer
-
May
-
M. G. Ancona and H. F. Tiersten. "Macroscopic physics of the silicon inversion layer," Phys. Rev. B, Condens. Matter, vol. 35, no. 15, pp. 7959-7965, May 1987.
-
(1987)
Phys. Rev. B, Condens. Matter
, vol.35
, Issue.15
, pp. 7959-7965
-
-
Ancona, M.G.1
Tiersten, H.F.2
-
38
-
-
2942579366
-
Multidimensional discretization of the stationary quantum drift-diffusion model for ultrasmall MOSFET structures
-
Jun
-
S. Odanaka, "Multidimensional discretization of the stationary quantum drift-diffusion model for ultrasmall MOSFET structures," IEEE Trans. Comput.-Aided Design Integr. Circuits Syst., vol. 23, no. 6, pp. 837-842, Jun. 2004.
-
(2004)
IEEE Trans. Comput.-Aided Design Integr. Circuits Syst
, vol.23
, Issue.6
, pp. 837-842
-
-
Odanaka, S.1
-
39
-
-
20344383924
-
Discretization scheme for the density-gradient equation and effect of boundary conditions
-
Oct
-
T.-W. Tang, X. Wang, and Y. Li, "Discretization scheme for the density-gradient equation and effect of boundary conditions," J. Comput. Electron., vol. 1, no. 3, pp. 389-393, Oct. 2002.
-
(2002)
J. Comput. Electron
, vol.1
, Issue.3
, pp. 389-393
-
-
Tang, T.-W.1
Wang, X.2
Li, Y.3
-
40
-
-
54249149841
-
Quantum aspects of resolving discrete charges in 'atomistic' device simulations
-
Dec
-
G. Roy, A. R. Brown, A. Asenov, and S. Roy, "Quantum aspects of resolving discrete charges in 'atomistic' device simulations," J. Comput. Electron., vol. 2, no. 2-4, pp. 323-327, Dec. 2003.
-
(2003)
J. Comput. Electron
, vol.2
, Issue.2-4
, pp. 323-327
-
-
Roy, G.1
Brown, A.R.2
Asenov, A.3
Roy, S.4
-
41
-
-
11044221347
-
A parallel adaptive finite volume method for nanoscale double-gate MOSFETs simulation
-
Mar
-
Y. Li and S.-M. Yu, "A parallel adaptive finite volume method for nanoscale double-gate MOSFETs simulation," J. Comput. Appl. Math., vol. 175, no. 1, pp. 87-99, Mar. 2005.
-
(2005)
J. Comput. Appl. Math
, vol.175
, Issue.1
, pp. 87-99
-
-
Li, Y.1
Yu, S.-M.2
-
42
-
-
0037416992
-
A novel parallel adaptive Monte Carlo method for nonlinear Poisson equation in semiconductor devices
-
Mar
-
Y. Li, H.-M. Lu, T.-W. Tang, and S. M. Sze, "A novel parallel adaptive Monte Carlo method for nonlinear Poisson equation in semiconductor devices," Math. Comput. Simulation, vol. 62, no. 3-6, pp. 413-420, Mar. 2003.
-
(2003)
Math. Comput. Simulation
, vol.62
, Issue.3-6
, pp. 413-420
-
-
Li, Y.1
Lu, H.-M.2
Tang, T.-W.3
Sze, S.M.4
-
43
-
-
0036361047
-
A practical implementation of parallel dynamic load balancing for adaptive computing in VLSI device simulation
-
Aug
-
Y. Li, S. M. Sze, and T. S. Chao, "A practical implementation of parallel dynamic load balancing for adaptive computing in VLSI device simulation," Eng. Comput., vol. 18, no. 2, pp. 124-137, Aug. 2002.
-
(2002)
Eng. Comput
, vol.18
, Issue.2
, pp. 124-137
-
-
Li, Y.1
Sze, S.M.2
Chao, T.S.3
-
44
-
-
0034516719
-
Mixed-mode device simulation
-
Dec
-
T. Grasser and S. Selberherr, "Mixed-mode device simulation," Microelectron. J., vol. 31, no. 11-12, pp. 873-881, Dec. 2000.
-
(2000)
Microelectron. J
, vol.31
, Issue.11-12
, pp. 873-881
-
-
Grasser, T.1
Selberherr, S.2
-
45
-
-
33846391334
-
A two-dimensional thin-film transistor simulation using adaptive computing technique
-
Jan
-
Y. Li, "A two-dimensional thin-film transistor simulation using adaptive computing technique," Appl. Math. Comput., vol. 184, no. 1, pp. 73-85, Jan. 2007.
-
(2007)
Appl. Math. Comput
, vol.184
, Issue.1
, pp. 73-85
-
-
Li, Y.1
-
46
-
-
0141952894
-
A time-domain approach to simulation and characterization of RF HBT two-tone intermodulation distortion
-
Oct
-
K.-Y. Huang, Y. Li, and C.-P. Lee, "A time-domain approach to simulation and characterization of RF HBT two-tone intermodulation distortion," IEEE Trans. Microw. Theory Tech., vol. 51, no. 10, pp. 2055-2062, Oct. 2003.
-
(2003)
IEEE Trans. Microw. Theory Tech
, vol.51
, Issue.10
, pp. 2055-2062
-
-
Huang, K.-Y.1
Li, Y.2
Lee, C.-P.3
-
47
-
-
37249059920
-
Effect of single grain boundary position on surrounding-gate polysilicon thin film transistors
-
Y. Li, J.-Y. Huang, and B.-S. Lee, "Effect of single grain boundary position on surrounding-gate polysilicon thin film transistors," Semicond. Sci. and Technology, vol. 23, pp. 015019-015019, 2008.
-
(2008)
Semicond. Sci. and Technology
, vol.23
, pp. 015019-015019
-
-
Li, Y.1
Huang, J.-Y.2
Lee, B.-S.3
-
49
-
-
44949227132
-
MOSFET performance scalingpart I: Historical trends
-
Jun
-
A. Khakifirooz and D. A. Antoniadis, "MOSFET performance scalingpart I: Historical trends," IEEE Trans. Electron Device, vol. 55, no. 6, pp. 1391-1400, Jun. 2008.
-
(2008)
IEEE Trans. Electron Device
, vol.55
, Issue.6
, pp. 1391-1400
-
-
Khakifirooz, A.1
Antoniadis, D.A.2
|