Discrete dopant fluctuations in 20-nm/15-nm-gate planar CMOS

IEEE Transactions on Electron Devices

Volumn 55, Issue 6, 2008, Pages 1449-1455

  Li, Yiming ^a   Yu, Shao Ming ^a   Hwang, Jiunn Ren ^b   Yang, Fu Liang ^b  

^a NATIONAL CHIAO TUNG UNIVERSITY   (Taiwan)

^b TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY   (Taiwan)

Author keywords

3 D modeling and simulation; Complementary metal oxide semiconductor (CMOS) device; Dopant concentration variation; Dopant position fluctuation; Random dopant distribution (RDD); Threshold voltage fluctuation

Indexed keywords

CARRIER TRANSPORT; COMPUTER SIMULATION; DOPING (ADDITIVES); THRESHOLD VOLTAGE;

DOPANT CONCENTRATION VARIATION; DOPANT POSITION FLUCTUATION; RANDOM DOPANT DISTRIBUTION (RDD); THRESHOLD VOLTAGE FLUCTUATION;

CMOS INTEGRATED CIRCUITS;

EID: 44949159936     PISSN: 00189383     EISSN: None     Source Type: Journal    
DOI: 10.1109/TED.2008.921991     Document Type: Article

References (21)

1. F.-L. Yang, D.-H. Lee, H.-Y. Chen, C.-Y. Chang, S.-D. Liu, C.-C. Huang, T.-X. Chung, H.-W. Chen, C.-C. Huang, Y.-H. Liu, C.-C.Wu, C.-C. Chen, S.-C. Chen, Y.-T. Chen, Y.-H. Chen, C.-J. Chen, B.-W. Chan, P.-F. Hsu, J.-H. Shieh, H.-J. Tao, Y.-C. Yeo, Y. Li, J.-W. Lee, P. Chen, M.-S. Liang, and C. Hu, "5 nm-gate nanowire FinFET," in VLSI Symp. Tech. Dig., 2004, pp. 196-197.
2. F.-L. Yang, H.-Y. Chen, F.-C. Chen, C.-C. Huang, C.-Y. Chang, H.-K. Chiu, C.-C. Lee, C.-C. Chen, H.-T. Huang, C.-J. Chen, H.-J. Tao, Y.-C. Yeo, M.-S. Liang, and C. Hu, "25 nm CMOS omega FETs," in IEDM Tech. Dig., 2002, pp. 255-258.
3. F.-L. Yang, J.-R. Hwang, and Y. Li, "Electrical characteristic fluctuations in sub-45 nm CMOS devices," in Proc. IEEE CICC, 2006, pp. 691-694.
4. H. Fukutome, Y. Momiyama, T. Kubo, E. Yoshida, H. Morioka, M. Tajima, and T. Aoyama, "Suppression of poly-gate-induced fluctuations in carrier profiles of sub-50 nm MOSFETs," in IEDM Tech. Dig., 2006, pp. 281-284.
5. A. Asenov, "Random dopant induced threshold voltage lowering and fluctuations in sub-0.1 μm MOSFET's: A 3-D 'atomistic' simulation study," IEEE Trans. Electron Devices, vol. 45, no. 12, pp. 2505-2513, Dec. 1998.
6. A. Asenov, A. R. Brown, J. H. Davies, S. Kaya, and G. Slavcheva, "Simulation of intrinsic parameter fluctuations in decananometer and nanometer-scale MOSFETs," IEEE Trans. Electron Devices, vol. 50, no. 9, pp. 1837-1852, Sep. 2003.
7. D. J. Frank, Y. Taur,M. Ieong, and H.-S. P.Wong, "Monte Carlo modeling of threshold variation due to dopant fluctuations," in VLSI Symp. Tech. Dig., 1999, pp. 169-170.
8. G. Roy, A. R. Brown, F. Adamu-Lema, S. Roy, and A. Asenov, "Simulation study of individual and combined sources of intrinsic parameter fluctuations in conventional nano-MOSFETs," IEEE Trans. Electron Devices, vol. 53, no. 12, pp. 3063-3070, Dec. 2006.
9. S. Xiong and J. Bokor, "A simulation study of gate line edge roughness effects on doping profiles of short-channel MOSFET devices," IEEE Trans. Electron Devices, vol. 51, no. 2, pp. 228-232, Feb. 2004.
10. Y. Li and S.-M. Yu, "Comparison of random-dopant-induced threshold voltage fluctuation in nanoscale single-, double-, and surrounding-gate field-effect transistors," Jpn. J. Appl. Phys., vol. 45, no. 9A, pp. 6860-6865, Sep. 2006.
11. Y. Li and S.-M. Yu, "Study of threshold voltage fluctuations of nanoscale double gate metal-oxide-semiconductor field effect transistors using quantum correction simulation," J. Comput. Electron., vol. 5, no. 2/3, pp. 125-129, Jul. 2006.
12. Y. Li, S.-M. Yu, and H.-M. Chen, "Process-variation- and randomdopants-induced threshold voltage fluctuations in nanoscale CMOS and SOI devices," Microelectron. Eng., vol. 84, no. 9/10, pp. 2117-2120, Sep./Oct. 2007.
13. Y. Li and S.-M. Yu, "Quantum correction simulation of random dopant-induced threshold voltage fluctuations in nanoscale metal-oxide-semiconductor structures," in Proc. 5th IEEE NANO, 2005, pp. 527-530.
14. A. Asenov and S. Saini, "Suppression of random dopant-induced threshold voltage fluctuations in sub-0.1-μm MOSFET's with epitaxial and δ-doped channels," IEEE Trans. Electron Devices, vol. 46, no. 8, pp. 1718-1724, Aug. 1999.
15. T. Taur and T. H. Ning, Fundamentals of Modern VLSI Devices. Cambridge, U.K.: Cambridge Univ. Press, 1998.
16. Y. Li, S. M. Sze, and T.-S. Chao, "A practical implementation of parallel dynamic load balancing for adaptive computing in VLSI device simulation," Eng. Comput., vol. 18, no. 2, pp. 124-137, Aug. 2002.
17. Y. Li, H.-M. Chou, and J.-W. Lee, "Investigation of electrical characteristics on surrounding-gate and omega-shaped-gate nanowire FinFETs," IEEE Trans. Nanotechnol., vol. 4, no. 5, pp. 510-516, Sep. 2005.
18. A. Martinez, J. R. Barker, M. P. Anantram, A. Svizhenko, and A. Asenov, "Developing a full 3D NEGF simulator with random dopant and interface roughness," in Proc. 11th Int. Workshop Comput. Electron., 2006, p. 275.
19. J. R. Watling, A. R. Brown, A. Asenov, A. Svizhenko, and M. P. Anantram, "Simulation of direct source-to-drain tunnelling using the density gradient formalism: Non-equilibrium Green's function calibration," in Proc. SISPAD, 2002, pp. 267-270.
20. S. Selberherr, Analysis and Simulation of Semiconductor Devices. New York: Springer-Verlag, 1984.
21. M. N. Darwish, J. L. Lentz, M. R. Pinto, P. M. Zeitzoff, T. J. Krutsick, and H. H. Vuong, "An improved electron and hole mobility model for general purpose device simulation," IEEE Trans. Electron Devices, vol. 44, no. 9, pp. 1529-1538, Sep. 1997.