5nm-gate nanowire FinFET

Digest of Technical Papers - Symposium on VLSI Technology

Volumn , Issue , 2004, Pages 196-197

  Yang, Fu Liang ^a   Lee, Di Hong ^a   Chen, Hou Yu ^a   Chang, Chang Yun ^a   Liu, Sheng Da ^a   Huang, Cheng Chuan ^a   Chung, Tang Xuan ^a   Chen, Hung Wei ^a   Huang, Chien Chao ^a   Liu, Yi Hsuan ^a   Wu, Chung Cheng ^a   Chen, Chi Chun ^a   Chen, Shih Chang ^a   Chen, Ying Tsung ^a   Chen, Ying Ho ^a   Chen, Chih Jian ^a   Chan, Bor Wen ^a   Hsu, Peng Fu ^a   Shieh, Jyu Horng ^a   Tao, Han Jan ^a   Yeo, Yee Chia ^a   Li, Yiming ^b   Lee, Jam Wem ^b   Chen, Pu ^b   Liang, Mong Song ^a   Hu, Chenming ^a   more..

^a TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY   (Taiwan)

^b NATIONAL CHIAO TUNG UNIVERSITY   (Taiwan)

Author keywords

[No Author keywords available]

Indexed keywords

ANNEALING; CARRIER CONCENTRATION; FABRICATION; LEAKAGE CURRENTS; PARAMETER ESTIMATION; QUANTUM THEORY; SCANNING ELECTRON MICROSCOPY; SILICON; THRESHOLD VOLTAGE; TRANSMISSION ELECTRON MICROSCOPY;

CRITICAL PROCESS SIMULATORS; GATE ELECTRODES; GATE TRANSISTORS; MECHANICAL SIMULATION;

CMOS INTEGRATED CIRCUITS;

EID: 4544367603     PISSN: 07431562     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (8)

1. B. Yu et al., IEDM 2002, pp. 251.
2. B. Doris et al., IEDM 2003, pp. 631.
3. B. Doris et al., IEDM 2002, pp. 267.
4. H. Wakabayashi et al., IEDM 2003, pp. 989.
5. B. Doyle et al., Symp. on VLSI Technology 2003, pp. 133.
6. F.- L. Yang et al., IEDM 2002, pp. 255.
7. F.-L. Yang et al., Symp. on VLSI Technology 2002, pp. 104.
8. Y. Li et al., unpublished.