Process-variation- and random-dopants-induced threshold voltage fluctuations in nanoscale CMOS and SOI devices

Microelectronic Engineering

Volumn 84, Issue 9-10, 2007, Pages 2117-2120

  Li, Yiming ^a   Yu, Shao Ming ^a   Chen, Hung Ming ^b  

^a NATIONAL CHIAO TUNG UNIVERSITY   (Taiwan)

^b TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY   (Taiwan)

Author keywords

Gate length deviation; Line edge roughness; Modeling and simulation; Process variation; Random dopant; Threshold voltage fluctuation

Indexed keywords

CMOS INTEGRATED CIRCUITS; DOPING (ADDITIVES); ION IMPLANTATION; MOSFET DEVICES; SILICON ON INSULATOR TECHNOLOGY;

GATE LENGTH DEVIATION; LINE EDGE ROUGHNESS; PROCESS VARIATION; RANDOM DOPANTS; THRESHOLD VOLTAGE FLUCTUATION;

THRESHOLD VOLTAGE;

EID: 34248644874     PISSN: 01679317     EISSN: None     Source Type: Journal    
DOI: 10.1016/j.mee.2007.04.059     Document Type: Article

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