-
1
-
-
0036147278
-
A practical architecture for reliable quantum computers
-
Jan.
-
M. Oskin, F. T. Chong, and I. L. Chuang, "A practical architecture for reliable quantum computers," IEEE Computer, vol. 35, no. 1, pp. 79-87, Jan. 2002.
-
(2002)
IEEE Computer
, vol.35
, Issue.1
, pp. 79-87
-
-
Oskin, M.1
Chong, F.T.2
Chuang, I.L.3
-
2
-
-
0028114541
-
Molecular computation of solutions to combinatorial problems
-
November
-
L. Adleman, "Molecular computation of solutions to combinatorial problems," Science, vol. 266, no. 5187, pp. 1021-1024, November 1994.
-
(1994)
Science
, vol.266
, Issue.5187
, pp. 1021-1024
-
-
Adleman, L.1
-
3
-
-
0035900398
-
Spintronics: A spin-based electronics vision for the future
-
S. A. Wolf, D. D. Awschalom, R. A. Buhrman, J. M. Daughton, S. von Molnar, M. L. Roukes, A. Y. Chtchelkanova, and D. M. Treger, "Spintronics: A Spin-Based Electronics Vision for the Future," Science, vol. 294, no. 5546, pp. 1488-1495, 2001.
-
(2001)
Science
, vol.294
, Issue.5546
, pp. 1488-1495
-
-
Wolf, S.A.1
Awschalom, D.D.2
Buhrman, R.A.3
Daughton, J.M.4
Von Molnar, S.5
Roukes, M.L.6
Chtchelkanova, A.Y.7
Treger, D.M.8
-
5
-
-
84860026458
-
Economies of cmos scaling
-
NIST, March
-
H. Stork, "Economies of cmos scaling," in VLSI Metrology Conference. NIST, March 2005, http://www.eeel.nist.gov/812/conference/2005. Talks/Stork.pdf.
-
(2005)
VLSI Metrology Conference
-
-
Stork, H.1
-
6
-
-
33751415010
-
Technology acceleration and the economics of lithography (cost containment and roi)
-
W. Trybula, "Technology acceleration and the economics of lithography (cost containment and roi)," Future Fab Intl., vol. 14, no. 19, 2003.
-
(2003)
Future Fab Intl.
, vol.14
, Issue.19
-
-
Trybula, W.1
-
7
-
-
0036907236
-
Molecular electronics: Devices, systems and tools for gigagate, gigabit chips
-
Nov.
-
M. Butts, A. DeHon, and S. Goldstein, "Molecular electronics: Devices, systems and tools for gigagate, gigabit chips," in ICCAD-2002, Nov. 2002.
-
(2002)
ICCAD-2002
-
-
Butts, M.1
Dehon, A.2
Goldstein, S.3
-
8
-
-
0038158890
-
Layout impact of resolution enhancement techniques: Impediment or opportunity?
-
New York, NY, USA: ACM Press
-
L. W. Liebmann, "Layout impact of resolution enhancement techniques: impediment or opportunity?" in ISPD '03: Proceedings of the 2003 international symposium on Physical design. New York, NY, USA: ACM Press, 2003, pp. 110-117.
-
(2003)
ISPD '03: Proceedings of the 2003 International Symposium on Physical Design
, pp. 110-117
-
-
Liebmann, L.W.1
-
9
-
-
4444224690
-
Toward a methodology for manufacturability driven design rule exploration
-
June
-
L. Capodieci, P. Gupta, A. B. Kahng, D. Sylvester, and J. Yang, "Toward a methodology for manufacturability driven design rule exploration," in Proc.ACM/IEEE Design Automation Conf, June 2004, pp. 311-316.
-
(2004)
Proc.ACM/IEEE Design Automation Conf
, pp. 311-316
-
-
Capodieci, L.1
Gupta, P.2
Kahng, A.B.3
Sylvester, D.4
Yang, J.5
-
11
-
-
0034831414
-
Impact of ret on physical layouts
-
New York, NY, USA: ACM Press
-
F. M. Schellenberg and L. Capodieci, "Impact of ret on physical layouts," in ISPD '01: Proceedings of the 2001 international symposium on Physical design. New York, NY, USA: ACM Press, 2001, pp. 52-55.
-
(2001)
ISPD '01: Proceedings of the 2001 International Symposium on Physical Design
, pp. 52-55
-
-
Schellenberg, F.M.1
Capodieci, L.2
-
12
-
-
3042571227
-
The importance of layout density control in semiconductor manufacturing
-
IEEE CS Press, April
-
V. Singh, "The importance of layout density control in semiconductor manufacturing," in Proc. Electronic Design Processes Workshop. IEEE CS Press, April 2003, pp. 70-74.
-
(2003)
Proc. Electronic Design Processes Workshop
, pp. 70-74
-
-
Singh, V.1
-
14
-
-
0038716770
-
Advanced routing in changing technology landscapes
-
Monterey, CA, USA, Apr.
-
H. K.-S. Leung, "Advanced routing in changing technology landscapes," in Proceedings of the 2003 International Symposium on Physical Design (ISPD'03), Monterey, CA, USA, Apr. 2003, pp. 118-121.
-
(2003)
Proceedings of the 2003 International Symposium on Physical Design (ISPD'03)
, pp. 118-121
-
-
Leung, H.K.-S.1
-
15
-
-
33751416590
-
The next implementation fabric: Issues and considerations
-
May
-
A. B. Kahng, "The next implementation fabric: Issues and considerations," FPGA and Programmable Logic Journal, vol. 3, no. 7, May 2004.
-
(2004)
FPGA and Programmable Logic Journal
, vol.3
, Issue.7
-
-
Kahng, A.B.1
-
16
-
-
0042635594
-
Exploring regular fabrics to optimize the performance-cost trade-off
-
New York, NY, USA: ACM Press
-
L. Pileggi, H. Schmit, A. J. Strojwas, P. Gopalakrishnan, V. Kheterpal, A. Koorapaty, C. Patel, V. Rovner, and K. Y. Tong, "Exploring regular fabrics to optimize the performance-cost trade-off," in DAC '03: Proceedings of the 40th conference on Design automation. New York, NY, USA: ACM Press, 2003, pp. 782-787.
-
(2003)
DAC '03: Proceedings of the 40th Conference on Design Automation
, pp. 782-787
-
-
Pileggi, L.1
Schmit, H.2
Strojwas, A.J.3
Gopalakrishnan, P.4
Kheterpal, V.5
Koorapaty, A.6
Patel, C.7
Rovner, V.8
Tong, K.Y.9
-
17
-
-
84860029966
-
The "missing link" of SoC design - Platform and structured ASICs
-
Editorial. [Online]
-
J. Lipman, "The "missing link" of SoC design - platform and structured ASICs," Editorial, SemiView, an Application Adaptable IC Newsletter. [Online]. Available: http://www.semiview.com/articles/v1- 3_missinglink.php
-
SemiView, an Application Adaptable IC Newsletter
-
-
Lipman, J.1
-
18
-
-
0033614026
-
"Dip-Pen" nanolithography
-
R. D. Piner, J. Zhu, F. Xu, S. Hong, and C. A. Mirkin, ""Dip-Pen" Nanolithography," Science, vol. 283, no. 5402, pp. 661-663, 1999.
-
(1999)
Science
, vol.283
, Issue.5402
, pp. 661-663
-
-
Piner, R.D.1
Zhu, J.2
Xu, F.3
Hong, S.4
Mirkin, C.A.5
-
19
-
-
0036541364
-
A mems nanoplotter with high-density parallel dip-pen nanolithography probe arrays
-
M. Zhang, D. Bullen, S. Chung, S. Hong, K. Ryu, Z. Fan, C. Mirkin, and C. Liu, "A mems nanoplotter with high-density parallel dip-pen nanolithography probe arrays," Nanotechnology, vol. 13, pp. 212-217, 2002.
-
(2002)
Nanotechnology
, vol.13
, pp. 212-217
-
-
Zhang, M.1
Bullen, D.2
Chung, S.3
Hong, S.4
Ryu, K.5
Fan, Z.6
Mirkin, C.7
Liu, C.8
-
20
-
-
4344561529
-
Design, fabrication, and characterization of thermally actuated probes arrays for dip pen nanolithography
-
D. Bullen, X. Wang, J. Zou, S. Chung, C. Mirkin, and C. Liu, "Design, fabrication, and characterization of thermally actuated probes arrays for dip pen nanolithography," J of Microelectrmechanical Systems, vol. 13, no. 4, pp. 594-602, 2004.
-
(2004)
J of Microelectrmechanical Systems
, vol.13
, Issue.4
, pp. 594-602
-
-
Bullen, D.1
Wang, X.2
Zou, J.3
Chung, S.4
Mirkin, C.5
Liu, C.6
-
21
-
-
4344679349
-
Unconventional nanofahrication
-
B. D. Gates, Q. Xu, J. C. Love, D. B. Wolfe, and G. M. Whitesides, "Unconventional nanofahrication," Annual Review of Materials Research, vol. 34, no. 1, pp. 339-372, 2004.
-
(2004)
Annual Review of Materials Research
, vol.34
, Issue.1
, pp. 339-372
-
-
Gates, B.D.1
Xu, Q.2
Love, J.C.3
Wolfe, D.B.4
Whitesides, G.M.5
-
22
-
-
0037418895
-
Ultrahigh-density nanowire lattices and circuits
-
N. A. Melosh, A. Boukai, F. Diana, B. Gerardot, A. Badolato, P. M. Petroff, and J. R. Heath, "Ultrahigh-Density Nanowire Lattices and Circuits," Science, vol. 300, no. 5616, pp. 112-115, 2003.
-
(2003)
Science
, vol.300
, Issue.5616
, pp. 112-115
-
-
Melosh, N.A.1
Boukai, A.2
Diana, F.3
Gerardot, B.4
Badolato, A.5
Petroff, P.M.6
Heath, J.R.7
-
23
-
-
0037117591
-
Supramolecular chemistry and self-assembly special feature: Beyond molecules: Self-assembly of mesoscopic and macroscopic components
-
G. M. Whitesides and M. Boncheva, "Supramolecular Chemistry And Self-assembly Special Feature: Beyond molecules: Self-assembly of mesoscopic and macroscopic components," PNAS, vol. 99, no. 8, pp. 4769-4774, 2002.
-
(2002)
PNAS
, vol.99
, Issue.8
, pp. 4769-4774
-
-
Whitesides, G.M.1
Boncheva, M.2
-
24
-
-
0242303136
-
Using self-assembly for the fabrication of nano-scale electronic and photonic devices
-
B. Amir Parviz, D. Ryan, and G. Whitesides, "Using self-assembly for the fabrication of nano-scale electronic and photonic devices," IEEE Transactions on Advanced Packaging, vol. 26, no. 3, pp. 233-241, 2003.
-
(2003)
IEEE Transactions on Advanced Packaging
, vol.26
, Issue.3
, pp. 233-241
-
-
Amir Parviz, B.1
Ryan, D.2
Whitesides, G.3
-
25
-
-
0141518628
-
Nanolithography using hierarchically assembled nanowire masks
-
D. Whang and C. M. Lieber, "Nanolithography using hierarchically assembled nanowire masks," Nano Letters, vol. 3, no. 7, pp. 951-4, 2003.
-
(2003)
Nano Letters
, vol.3
, Issue.7
, pp. 951-954
-
-
Whang, D.1
Lieber, C.M.2
-
26
-
-
33750911039
-
DNA-based artificial nanostructures: Fabrication, properties, and applications
-
H. S. Nalwa, Ed. American Scientific Publishers, ch. 5
-
Y. Sun and C.-H. Kiang, "DNA-based artificial nanostructures: Fabrication, properties, and applications," in Handbook of Nanostructured Biomaterials and Their Applications in Nanobiotechnology, H. S. Nalwa, Ed. American Scientific Publishers, 2005, ch. 5.
-
(2005)
Handbook of Nanostructured Biomaterials and Their Applications in Nanobiotechnology
-
-
Sun, Y.1
Kiang, C.-H.2
-
27
-
-
0034729029
-
Programming the assembly of two- And three-dimensional architectures with DNA and nanoscale inorganic building blocks
-
C. Mirkin, "Programming the Assembly of Two- and Three-Dimensional Architectures with DNA and Nanoscale Inorganic Building Blocks," Inorg. Chem., vol. 39, pp. 2258-72, 2000.
-
(2000)
Inorg. Chem.
, vol.39
, pp. 2258-2272
-
-
Mirkin, C.1
-
28
-
-
0035250210
-
DNA-directed assembly of gold nanowires on complementary surfaces
-
J. K. N. Mbindyo, B. R. Reiss, B. R. Martin, C. D. Keating, M. J. Natan, and T. E. Mallouk, "DNA-Directed Assembly of Gold Nanowires on Complementary Surfaces," Advanced Materials, vol. 13, pp. 249-254, 2001.
-
(2001)
Advanced Materials
, vol.13
, pp. 249-254
-
-
Mbindyo, J.K.N.1
Reiss, B.R.2
Martin, B.R.3
Keating, C.D.4
Natan, M.J.5
Mallouk, T.E.6
-
29
-
-
0345306761
-
DNA-templated carbon nanotube field-effect transistor
-
K. Keren, R. S. Berman, E. Buchstab, U. Sivan, and E. Braun, "DNA-Templated Carbon Nanotube Field-Effect Transistor," Science, vol. 302, no. 5649, pp. 1380-1382, 2003.
-
(2003)
Science
, vol.302
, Issue.5649
, pp. 1380-1382
-
-
Keren, K.1
Berman, R.S.2
Buchstab, E.3
Sivan, U.4
Braun, E.5
-
30
-
-
84874685888
-
4×4 dna tile and lattices: Characterization, self-assembly and metallization of a novel dna nanostructure motif
-
June
-
H. Yan, S. H. Park, L. Feng, J. Reif, and T. H. LaBean, "4×4 dna tile and lattices: Characterization, self-assembly and metallization of a novel dna nanostructure motif," in Ninth International Meeting on DNA Based Computers (DNA9), June 2003.
-
(2003)
Ninth International Meeting on DNA Based Computers (DNA9)
-
-
Yan, H.1
Park, S.H.2
Feng, L.3
Reif, J.4
LaBean, T.H.5
-
31
-
-
14044251445
-
Algorithmic self-assembly of dna sierpinski triangles
-
P. W. Rothemund, N. Papadakis, and E. Winfree, "Algorithmic self-assembly of dna sierpinski triangles," PLoS Biology, vol. 2, no. 12, p. e424, 2004.
-
(2004)
PLoS Biology
, vol.2
, Issue.12
-
-
Rothemund, P.W.1
Papadakis, N.2
Winfree, E.3
-
32
-
-
35048830893
-
Self-assembled circuit patterns
-
LNCS
-
M. Cook, P. W. Rothemund, and E. Winfree, "Self-assembled circuit patterns," in DNA Computers 9, vol. 2943, no. 91. LNCS, 2004, pp. 91-107.
-
(2004)
DNA Computers 9
, vol.2943
, Issue.91
, pp. 91-107
-
-
Cook, M.1
Rothemund, P.W.2
Winfree, E.3
-
33
-
-
33751425632
-
Introduction to self-assembling DNA nanostructures for computation and nanofabrication
-
J. T. L. Wang, C. H. Wu, and P. P. Wang, Eds. World Scientific Publishing, Singapore, ch. 2
-
T. H. LaBean, "Introduction to self-assembling DNA nanostructures for computation and nanofabrication," in Computational Biology and Genome Informatics, J. T. L. Wang, C. H. Wu, and P. P. Wang, Eds. World Scientific Publishing, Singapore, 2003, ch. 2.
-
(2003)
Computational Biology and Genome Informatics
-
-
LaBean, T.H.1
-
34
-
-
0037124873
-
Molecular electronics random access memory circuits
-
Y. Luo, C. Collier, K. Nielsen, J. Jeppesen, J. Perkins, E. Delonno, A. Pease, J. F. Stoddart, and J. R. Heath, "Molecular electronics random access memory circuits," ChemPhysChem, vol. 3, pp. 519-25, 2002.
-
(2002)
ChemPhysChem
, vol.3
, pp. 519-525
-
-
Luo, Y.1
Collier, C.2
Nielsen, K.3
Jeppesen, J.4
Perkins, J.5
Delonno, E.6
Pease, A.7
Stoddart, J.F.8
Heath, J.R.9
-
35
-
-
0037392525
-
Nanoscale molecular-switch crossbar circuits
-
[Online]
-
Y. Chen, G.-Y. Jung, D. A. A. Ohlberg, X. Li, D. R. Stewart, J. O. Jeppesen, K. A. Nielsen, J. F. Stoddart, and R. S. Williams, "Nanoscale molecular-switch crossbar circuits," Nanotechnology, vol. 14, no. 4, pp. 462-468, 2003. [Online]. Available: http://stacks.iop.org/0957-4484/14/462
-
(2003)
Nanotechnology
, vol.14
, Issue.4
, pp. 462-468
-
-
Chen, Y.1
Jung, G.-Y.2
Ohlberg, D.A.A.3
Li, X.4
Stewart, D.R.5
Jeppesen, J.O.6
Nielsen, K.A.7
Stoddart, J.F.8
Williams, R.S.9
-
36
-
-
4143141855
-
Fabrication of a 34 × 34 crossbar structure at 50 nm half-pitch by uv-based nanoimprint lithography
-
July
-
G. Y. Jung, S. Ganapathiappan, D. A. A. Ohlberg, D. L. Olynick, Y. Chen, W. M. Tong, and R. S. Williams, "Fabrication of a 34 × 34 crossbar structure at 50 nm half-pitch by uv-based nanoimprint lithography," Nano Letters, vol. 4, no. 7, pp. 1225-1229, July 2004.
-
(2004)
Nano Letters
, vol.4
, Issue.7
, pp. 1225-1229
-
-
Jung, G.Y.1
Ganapathiappan, S.2
Ohlberg, D.A.A.3
Olynick, D.L.4
Chen, Y.5
Tong, W.M.6
Williams, R.S.7
-
37
-
-
0001405799
-
Nonvolatile memory and programmable logic from molecule-gated nanowires
-
X. Duan, Y. Huang, and C. Lieber, "Nonvolatile memory and programmable logic from molecule-gated nanowires," Nano Letters, vol. 2, no. 5, pp. 487-490, 2002.
-
(2002)
Nano Letters
, vol.2
, Issue.5
, pp. 487-490
-
-
Duan, X.1
Huang, Y.2
Lieber, C.3
-
38
-
-
2342633730
-
Direct observation of nanoscale switching centers in metal/molecule/metal structures
-
April
-
C. N. Lau, D. R. Stewart, R. S. Williams, and M. Bockrath, "Direct observation of nanoscale switching centers in metal/molecule/metal structures," Nano Letters, vol. 4, no. 4, pp. 569-572, April 2004.
-
(2004)
Nano Letters
, vol.4
, Issue.4
, pp. 569-572
-
-
Lau, C.N.1
Stewart, D.R.2
Williams, R.S.3
Bockrath, M.4
-
39
-
-
0034682887
-
A [2]catenane-based solid state electronically reconfigurable switch
-
C. P. Collier, G. Mattersteig, E. W. Wong, Y. Luo, K. Beverly, J. Sampaio, F. M. Raymo, J. F. Stoddart, and J. R. Heath, "A [2]Catenane-Based Solid State Electronically Reconfigurable Switch," Science, vol. 289, no. 5482, pp. 1172-1175, 2000.
-
(2000)
Science
, vol.289
, Issue.5482
, pp. 1172-1175
-
-
Collier, C.P.1
Mattersteig, G.2
Wong, E.W.3
Luo, Y.4
Beverly, K.5
Sampaio, J.6
Raymo, F.M.7
Stoddart, J.F.8
Heath, J.R.9
-
40
-
-
0034617249
-
Carbon nanotube based nonvolatile random access memory for molecular computing
-
T. Rueckes, K. Kim, E. Joselevich, G. Tseng, C. Cheung, and C. Lieber, "Carbon nanotube based nonvolatile random access memory for molecular computing," Science, vol. 289, pp. 94-97, 2000.
-
(2000)
Science
, vol.289
, pp. 94-97
-
-
Rueckes, T.1
Kim, K.2
Joselevich, E.3
Tseng, G.4
Cheung, C.5
Lieber, C.6
-
42
-
-
0031362699
-
Defect tolerance on the Teramac custom computer
-
Napa Valley, CA, April 16-18
-
B. Culbertson, R. Amerson, R. Carter, P. Kuekes, and G. Snider, "Defect tolerance on the Teramac custom computer," in Proceedings of the 1997 IEEE Symposium on FPGA's for Custom Computing Machines (FCCM '97), Napa Valley, CA, April 16-18 1997.
-
(1997)
Proceedings of the 1997 IEEE Symposium on FPGA's for Custom Computing Machines (FCCM '97)
-
-
Culbertson, B.1
Amerson, R.2
Carter, R.3
Kuekes, P.4
Snider, G.5
-
43
-
-
0032510985
-
A defect-tolerant computer architecture: Opportunities for nanotechnology
-
12 June
-
J. R. Heath, P. J. Kuekes, G. S. Snider, and R. S. Williams, "A defect-tolerant computer architecture: Opportunities for nanotechnology," Science, vol. 280, pp. 1716-1721, 12 June 1998.
-
(1998)
Science
, vol.280
, pp. 1716-1721
-
-
Heath, J.R.1
Kuekes, P.J.2
Snider, G.S.3
Williams, R.S.4
-
45
-
-
0036608520
-
Fault-tolerant techniques for nanocomputers
-
[Online]
-
K. Nikolic, A. Sadek, and M. Forshaw, "Fault-tolerant techniques for nanocomputers," Nanotechnology, vol. 13, no. 3, pp. 357-362, 2002. [Online]. Available: http://stacks.iop.org/0957-4484/13/357
-
(2002)
Nanotechnology
, vol.13
, Issue.3
, pp. 357-362
-
-
Nikolic, K.1
Sadek, A.2
Forshaw, M.3
-
47
-
-
0032510985
-
A defect-tolerant computer architecture: Opportunities for nanotechnology
-
J. Heath, P. Kuekes, G. Snider, and R. Williams, "A defect-tolerant computer architecture: Opportunities for nanotechnology," Science, vol. 280, p. 1716, 1998.
-
(1998)
Science
, vol.280
, pp. 1716
-
-
Heath, J.1
Kuekes, P.2
Snider, G.3
Williams, R.4
-
49
-
-
0141499770
-
Array-based architecture for FET-based, nanoscale electronics
-
Mar.
-
A. DeHon, "Array-based architecture for FET-based, nanoscale electronics," IEEE Transactions on Nanotechnology, vol. 2, no. 1, pp. 23-32, Mar. 2003.
-
(2003)
IEEE Transactions on Nanotechnology
, vol.2
, Issue.1
, pp. 23-32
-
-
DeHon, A.1
-
50
-
-
4544286478
-
Circuit and system architecture for dna-guided self-assembly of nanoelectronics
-
April
-
J. Patwardhan, C. Dwyer, A. Lebeck, and D. Sorin, "Circuit and system architecture for dna-guided self-assembly of nanoelectronics," in Proceedings of the 1st Conference on the Foundations of Nanoscience: Self-Assembled Architectures and Devices, April 2004, pp. 344-358.
-
(2004)
Proceedings of the 1st Conference on the Foundations of Nanoscience: Self-assembled Architectures and Devices
, pp. 344-358
-
-
Patwardhan, J.1
Dwyer, C.2
Lebeck, A.3
Sorin, D.4
-
51
-
-
4344644019
-
Cmos-like logic in defective, nanoscale crossbars
-
[Online]
-
G. Snider, P. Kuekes, and R. S. Williams, "Cmos-like logic in defective, nanoscale crossbars," Nanotechnology, vol. 15, no. 8, pp. 881-891, 2004. [Online]. Available: http://stacks.iop.org/0957-4484/15/881
-
(2004)
Nanotechnology
, vol.15
, Issue.8
, pp. 881-891
-
-
Snider, G.1
Kuekes, P.2
Williams, R.S.3
-
52
-
-
0041633858
-
Parameter variations and impact on circuits and microarchitecture
-
New York, NY, USA: ACM Press
-
S. Borkar, T. Karnik, S. Narendra, J. Tschanz, A. Keshavarzi, and V. De, "Parameter variations and impact on circuits and microarchitecture," in DAC '03: Proceedings of the 40th conference on Design automation. New York, NY, USA: ACM Press, 2003, pp. 338-342.
-
(2003)
DAC '03: Proceedings of the 40th Conference on Design Automation
, pp. 338-342
-
-
Borkar, S.1
Karnik, T.2
Narendra, S.3
Tschanz, J.4
Keshavarzi, A.5
De, V.6
-
53
-
-
27944486592
-
Variation-tolerant circuits: Circuit solutions and techniques
-
New York, NY, USA: ACM Press
-
J. Tschanz, K. Bowman, and V. De, "Variation-tolerant circuits: circuit solutions and techniques," in DAC '05: Proceedings of the 42nd annual conference on Design automation. New York, NY, USA: ACM Press, 2005. pp. 762-763.
-
(2005)
DAC '05: Proceedings of the 42nd Annual Conference on Design Automation
, pp. 762-763
-
-
Tschanz, J.1
Bowman, K.2
De, V.3
-
54
-
-
0036474722
-
Impact of die-to-die and within-die parameter fluctuations on the maximum clock frequency distribution for gigascale integration
-
Feb.
-
K. A. Bowman and J. D. Meindl, "Impact of die-to-die and within-die parameter fluctuations on the maximum clock frequency distribution for gigascale integration," IEEE JSSC, vol. 37, no. 2, Feb. 2002.
-
(2002)
IEEE JSSC
, vol.37
, Issue.2
-
-
Bowman, K.A.1
Meindl, J.D.2
-
55
-
-
1342323840
-
An integrated environment for technology closure of deep-submicron IC designs
-
January-February
-
L. Trevillyan, D. Kung, R. Puri, L. N. Reddy, and M. A. Kazda, "An integrated environment for technology closure of deep-submicron IC designs," IEEE Design and Test of Computers, pp. 14-22, January-February 2004.
-
(2004)
IEEE Design and Test of Computers
, pp. 14-22
-
-
Trevillyan, L.1
Kung, D.2
Puri, R.3
Reddy, L.N.4
Kazda, M.A.5
-
56
-
-
0033717865
-
Clock rate versus ipc: The end of the road for conventional microarchitectures
-
New York, NY, USA: ACM Press
-
V. Agarwal, M. S. Hrishikesh, S. W. Keckler, and D. Burger, "Clock rate versus ipc: the end of the road for conventional microarchitectures," in ISCA '00: Proceedings of the 27th annual international symposium on Computer architecture. New York, NY, USA: ACM Press, 2000, pp. 248-259.
-
(2000)
ISCA '00: Proceedings of the 27th Annual International Symposium on Computer Architecture
, pp. 248-259
-
-
Agarwal, V.1
Hrishikesh, M.S.2
Keckler, S.W.3
Burger, D.4
-
57
-
-
0003705271
-
An introduction to asynchronous circuit design
-
Dept. of Computer Science, Sept.
-
A. Davis and S. M. Nowick, "An introduction to asynchronous circuit design," Dept. of Computer Science, University of Utah, Tech. Rep. UUCS-97-013, Sept. 1997.
-
(1997)
University of Utah, Tech. Rep.
, vol.UUCS-97-013
-
-
Davis, A.1
Nowick, S.M.2
-
58
-
-
0001337809
-
The limitations to delay-insensitivity in asynchronous circuits
-
Cambridge, MA, USA: MIT Press
-
A. J. Martin, "The limitations to delay-insensitivity in asynchronous circuits," in AUSCRYPT '90: Proceedings of the sixth MIT conference on Advanced research in VLSI. Cambridge, MA, USA: MIT Press, 1990, pp. 263-278.
-
(1990)
AUSCRYPT '90: Proceedings of the Sixth MIT Conference on Advanced Research in VLSI
, pp. 263-278
-
-
Martin, A.J.1
-
59
-
-
0033362680
-
Statistically optimized asynchronous barrel shifters for variable length codecs
-
Aug.
-
P. A. Beerel, S. Kim, P.-C. Yeh, and K. Kim, "Statistically optimized asynchronous barrel shifters for variable length codecs," in International Symposium on Low Power Electronics and Design, Aug. 1999, pp. 261-263.
-
(1999)
International Symposium on Low Power Electronics and Design
, pp. 261-263
-
-
Beerel, P.A.1
Kim, S.2
Yeh, P.-C.3
Kim, K.4
-
60
-
-
0036294823
-
Power and performance evaluation of globally asynchronous locally synchronous processors
-
Washington, DC, USA: IEEE Computer Society
-
A. Iyer and D. Marculescu, "Power and performance evaluation of globally asynchronous locally synchronous processors," in ISCA '02: Proceedings of the 29th annual international symposium on Computer architecture. Washington, DC, USA: IEEE Computer Society, 2002, pp. 158-168.
-
(2002)
ISCA '02: Proceedings of the 29th Annual International Symposium on Computer Architecture
, pp. 158-168
-
-
Iyer, A.1
Marculescu, D.2
-
61
-
-
28444449170
-
System level power and performance modeling of GALS point-to-point communication interfaces
-
San Diego, CA, Aug.
-
K. Niyogi and D. Marculescu, "System level power and performance modeling of GALS point-to-point communication interfaces," in Proceedings of the 2005 International Symposium on Law Power Electronics and Design (ISLPED'05), San Diego, CA, Aug. 2005, pp. 381-386.
-
(2005)
Proceedings of the 2005 International Symposium on Law Power Electronics and Design (ISLPED'05)
, pp. 381-386
-
-
Niyogi, K.1
Marculescu, D.2
-
62
-
-
8744277752
-
A case for asynchronous computer architecture
-
June [Online]
-
R. Manohar, "A case for asynchronous computer architecture," in the ISCA Workshop on Complexity-Effective Design, June 2000. [Online]. Available: http://vlsi.cornell.edu/~rajit/abstracts/async-case.html
-
(2000)
The ISCA Workshop on Complexity-effective Design
-
-
Manohar, R.1
-
63
-
-
0033079548
-
Designing asynchronous circuits for low power: An ifir filter bank for a digital hearing aid
-
IEEE Computer Society Press, Feb.
-
L. S. Nielsen and J. Sparsø, "Designing asynchronous circuits for low power: an ifir filter bank for a digital hearing aid," in Proceedings of IEEE, vol. 87, no. 2. IEEE Computer Society Press, Feb. 1999, pp. 268-281.
-
(1999)
Proceedings of IEEE
, vol.87
, Issue.2
, pp. 268-281
-
-
Nielsen, L.S.1
Sparsø, J.2
-
64
-
-
0035247709
-
An asynchronous instruction length decoder
-
Feb.
-
K. S. Stevens, S. Rotem, R. Ginosar, P. Beerel, C. J. Myers, K. Y. Yun, R. Koi, C. Dike, and M. Roncken, "An asynchronous instruction length decoder," IEEE Journal of Solid-State Circuits, vol. 36, no. 2, pp. 217-228, Feb. 2001.
-
(2001)
IEEE Journal of Solid-state Circuits
, vol.36
, Issue.2
, pp. 217-228
-
-
Stevens, K.S.1
Rotem, S.2
Ginosar, R.3
Beerel, P.4
Myers, C.J.5
Yun, K.Y.6
Koi, R.7
Dike, C.8
Roncken, M.9
-
65
-
-
0036508274
-
Power-constrained cmos scaling limits
-
D. J. Frank, "Power-constrained cmos scaling limits." IBM Journal of Research and Development, vol. 46, no. 2-3, pp. 235-344, 2002.
-
(2002)
IBM Journal of Research and Development
, vol.46
, Issue.2-3
, pp. 235-344
-
-
Frank, D.J.1
-
66
-
-
22944492681
-
Microprocessor design issues: Thoughts on the road ahead
-
May
-
M. J. Flynn and P. Hung, "Microprocessor design issues: Thoughts on the road ahead," IEEE Micro, vol. 25, no. 3, pp. 16-31, May 2005.
-
(2005)
IEEE Micro
, vol.25
, Issue.3
, pp. 16-31
-
-
Flynn, M.J.1
Hung, P.2
-
67
-
-
27544466455
-
Intel's pc roadmap sees double
-
May 24
-
K. Krewell, "Intel's pc roadmap sees double," Microprocessor Report, May 24 2004.
-
(2004)
Microprocessor Report
-
-
Krewell, K.1
-
68
-
-
12844273425
-
Spatial computation
-
Boston, MA, October [Online]
-
M. Budiu, G. Venkataramani, T. Chelcea, and S. C. Goldstein, "Spatial computation," in International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS), Boston, MA, October 2004. [Online]. Available: http://www.cs.cmu.edu/~mihaib/research/ asplos04.pdf
-
(2004)
International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS)
-
-
Budiu, M.1
Venkataramani, G.2
Chelcea, T.3
Goldstein, S.C.4
-
69
-
-
12344330497
-
C to asynchronous dataflow circuits: An end-to-end toolflow
-
Temecula, CA, June [Online]
-
G. Venkataramani, M. Budiu, and S. C. Goldstein, "C to asynchronous dataflow circuits: An end-to-end toolflow," in International Workshop on Logic Syntheiss, Temecula, CA, June 2004. [Online]. Available: http://www.cs.cmu.edu/~mihaib/research/iwls04.pdf
-
(2004)
International Workshop on Logic Syntheiss
-
-
Venkataramani, G.1
Budiu, M.2
Goldstein, S.C.3
-
71
-
-
0018923294
-
Information transfer and area-time tradeoffs for vlsi multiplication
-
H. Abelson and P. Andreae, "Information transfer and area-time tradeoffs for vlsi multiplication," Communications of the ACM, vol. 23, no. 1, pp. 20-23, 1980.
-
(1980)
Communications of the ACM
, vol.23
, Issue.1
, pp. 20-23
-
-
Abelson, H.1
Andreae, P.2
-
73
-
-
84944033564
-
The chip complexity of binary arithmetic
-
Los Angeles, CA, USA
-
R. P. Brent and H. T. Kung, "The chip complexity of binary arithmetic," in Proc. Twelfth Annual ACM Symposium on Theory of Computing, Los Angeles, CA, USA, 1980, pp. 190-200.
-
(1980)
Proc. Twelfth Annual ACM Symposium on Theory of Computing
, pp. 190-200
-
-
Brent, R.P.1
Kung, H.T.2
-
74
-
-
84976738616
-
The area-time complexity of binary multiplication
-
_, "The area-time complexity of binary multiplication," Journal of the ACM, vol. 28, no. 3, pp. 521-534, 1981.
-
(1981)
Journal of the ACM
, vol.28
, Issue.3
, pp. 521-534
-
-
-
75
-
-
0031275325
-
Predicting cmos speed with gate oxide and voltage scaling and interconnect loading effects
-
Nov
-
K. Chen, C. Hu, P. Fang, R. Lin, and D. Wollesen, "Predicting cmos speed with gate oxide and voltage scaling and interconnect loading effects," IEEE Trans. Electron Devices, vol. 44, no. 11, pp. 1951-57, Nov 1997.
-
(1997)
IEEE Trans. Electron Devices
, vol.44
, Issue.11
, pp. 1951-1957
-
-
Chen, K.1
Hu, C.2
Fang, P.3
Lin, R.4
Wollesen, D.5
-
76
-
-
0032592098
-
Deep-submicron microprocessor design issues
-
July
-
M. J. Flynn, P. Hung, and K. W. Rudd, "Deep-submicron microprocessor design issues," IEEE Micro, July 1999.
-
(1999)
IEEE Micro
-
-
Flynn, M.J.1
Hung, P.2
Rudd, K.W.3
-
77
-
-
0034592573
-
Prediction of interconnect fan-out distribution using rent's rule
-
P. Zarkesh-Ha, J. A. Davis, W. Loh, and J. D. Meindl, "Prediction of interconnect fan-out distribution using rent's rule," in Proc. Int'l Workshop on System-level Interconnect Prediction (SLIP00), 2000, pp. 107-112.
-
(2000)
Proc. Int'l Workshop on System-level Interconnect Prediction (SLIP00)
, pp. 107-112
-
-
Zarkesh-Ha, P.1
Davis, J.A.2
Loh, W.3
Meindl, J.D.4
-
79
-
-
4444339042
-
"Timing closure through a globally synchronous, timing partitioned design methodology
-
A. Edman and C. Svensson, "Timing closure through a globally synchronous, timing partitioned design methodology," in Proc. ACM/IEEE Design Automation Conference, 2004, pp. 71-74.
-
(2004)
Proc. ACM/IEEE Design Automation Conference
, pp. 71-74
-
-
Edman, A.1
Svensson, C.2
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