An asynchronous instruction length decoder

IEEE Journal of Solid-State Circuits

Volumn 36, Issue 2, 2001, Pages 217-228

  Stevens, Kenneth S ^a,b   Rotem, Shai ^a,b   Ginosar, Ran ^a,c   Beerel, Peter ^a,d   Myers, Chris J ^a,e   Yun, Kenneth Y ^a,f   Kol, Rakefet ^a,c   Dike, Charles ^a,b   Roncken, Marly ^a,b  

^a IEEE   (United States)

^b INTEL CORPORATION   (United States)

^c TECHNION ISRAEL INSTITUTE OF TECHNOLOGY   (Israel)

^d University of Southern California ^*  (United States)

^e Department of Electrical and Computer Engineering   (United States)

^f UNIVERSITY OF CALIFORNIA   (United States)

Author keywords

Asynchronous debugging; Asynchronous design; Asynchronous testability; Domino circuits; Handshake protocols; Instruction length decoding; Pulsed logic; Relative timing; Self reset logic; Self timed

Indexed keywords

ASYNCHRONOUS SEQUENTIAL LOGIC; CMOS INTEGRATED CIRCUITS; DECODING; DESIGN FOR TESTABILITY; THROUGHPUT; TIME DIVISION MULTIPLE ACCESS;

ASYNCHRONOUS INSTRUCTION LENGTH DECODERS;

MICROPROCESSOR CHIPS;

EID: 0035247709     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/4.902762     Document Type: Article

References (27)

1. Asynchronous design methodologies: An overview
2. Relative timing
3. CAD directions for high-performance asynchronous circuits
4. Modeling and comparing CMOS implementations of the C-element
5. Average-case optimized technology mapping of one-hot domino circuits
6. Theoretical limits on the data dependent performance of asynchronous circuits
7. Bounding average time separations of events in stochastic timed petri nets with choice
8. System timing
9. Static timing analysis for self resetting circuits
10. Synthesis of asynchronous control circuits with automatically generated relative timing assumptions
11. Automatic synthesis of extended burst-mode circuits: Part I (specification and hazard-free implementation)
12. Automatic synthesis of extended burst-mode circuits: Part II (automatic synthesis)
13. COSMOS: A compiled simulator for MOS circuits
14. Defect-oriented testability for asynchronous ICs
15. CA-BIST for asynchronous circuits: A case study on the RAPPID asynchronous instruction length decoder
16. Quad DCVS dynamic logic fault modeling and testing
17. Detecting resistive shorts for CMOS domino circuits
18. Adaptive synchronization
19. Optimal clocking and enhanced testability for high-performance self-resetting domino pipelines
20. Verification of timed systems using POSETS
21. Timed circuit synthesis using implicit methods