-
3
-
-
0035834415
-
Logic gates and computation from assembled nanowire building blocks
-
Nov.
-
Y. Huang, X. Duan, Y. Cui, L. J. Lauhon, K.-H. Kim, and C. M. Lieber, "Logic gates and computation from assembled nanowire building blocks, " Science, vol. 294, pp. 1313-1317, Nov. 2001.
-
(2001)
Science
, vol.294
, pp. 1313-1317
-
-
Huang, Y.1
Duan, X.2
Cui, Y.3
Lauhon, L.J.4
Kim, K.-H.5
Lieber, C.M.6
-
4
-
-
0035834444
-
Logic circuits with carbon nanotube transistors
-
Nov.
-
A. Bachtold, P. Hadley, T. Nakanishi, and C. Dekker, "Logic circuits with carbon nanotube transistors," Science, vol. 294, pp. 1317-1320, Nov. 2001.
-
(2001)
Science
, vol.294
, pp. 1317-1320
-
-
Bachtold, A.1
Hadley, P.2
Nakanishi, T.3
Dekker, C.4
-
5
-
-
0033575366
-
Electronically configurable molecular-based logic gates
-
July
-
C. P. Collier, E. W. Wong, M. Belohradsky, F. M. Raymo, J. F. Stoddart, P. J. Kuekes, R. S. Williams, and J. R. Heath, "Electronically configurable molecular-based logic gates," Science, vol. 285, pp. 391-394, July 1999.
-
(1999)
Science
, vol.285
, pp. 391-394
-
-
Collier, C.P.1
Wong, E.W.2
Belohradsky, M.3
Raymo, F.M.4
Stoddart, J.F.5
Kuekes, P.J.6
Williams, R.S.7
Heath, J.R.8
-
7
-
-
0036102255
-
Digital logic using molecular electronics
-
San Francisco, CA, Feb.
-
S. C. Goldstein and D. Rosewater, "Digital logic using molecular electronics," in Proceedings of the 2002 IEEE International Solid-State Circuits Conference (ISSCC '02), San Francisco, CA, Feb. 2002. pp. 204-205.
-
(2002)
Proceedings of the 2002 IEEE International Solid-State Circuits Conference (ISSCC '02)
, pp. 204-205
-
-
Goldstein, S.C.1
Rosewater, D.2
-
8
-
-
0142226111
-
Molecules, gates, circuits, computers
-
M. A. Reed and T. Lee, Eds. 25650 North Lewis Way, Stevenson Ranch, California 91381-1439, USA: American Scientific Publishers, May
-
S. C. Goldstein and M. Budiu, "Molecules, gates, circuits, computers," in Molecular Nanoelectronics, M. A. Reed and T. Lee, Eds. 25650 North Lewis Way, Stevenson Ranch, California 91381-1439, USA: American Scientific Publishers, May 2003.
-
(2003)
Molecular Nanoelectronics
-
-
Goldstein, S.C.1
Budiu, M.2
-
9
-
-
0004962219
-
-
1730 Massachusetts Avenue, N.W., Washington, DC 20036-1903: Computer Society Press
-
V. D. Agrawal and S. C. Seth, Tutorial: Test Generation for VLSI Chips. 1730 Massachusetts Avenue, N.W., Washington, DC 20036-1903: Computer Society Press, 1988.
-
(1988)
Tutorial: Test Generation for VLSI Chips
-
-
Agrawal, V.D.1
Seth, S.C.2
-
10
-
-
0031655580
-
Universal fault diagnosis for lookup table FPGAs
-
January-March
-
T. Inoue, S. Miyazaki, and H. Fujiwara, "Universal fault diagnosis for lookup table FPGAs," IEEE Design and Test of Computers, vol. 15, no. 1, pp. 39-44, January-March 1998.
-
(1998)
IEEE Design and Test of Computers
, vol.15
, Issue.1
, pp. 39-44
-
-
Inoue, T.1
Miyazaki, S.2
Fujiwara, H.3
-
11
-
-
0033337090
-
Defect and fault tolerance FPGAs by in shifting the configuration data
-
Albuquerque, NM, USA, November 1-3
-
A. Doumar, S. Kaneko, and H. Ito, "Defect and fault tolerance FPGAs by in shifting the configuration data," in Proceedings of the International Symposium on Defect and Fault Tolerance in VLSI Systems, Albuquerque, NM, USA, November 1-3 1999, pp. 377-385.
-
(1999)
Proceedings of the International Symposium on Defect and Fault Tolerance in VLSI Systems
, pp. 377-385
-
-
Doumar, A.1
Kaneko, S.2
Ito, H.3
-
12
-
-
0029710665
-
On the diagnosis of programmable interconnect systems: Theory and application
-
April 28-May 1
-
W. K. Huang, X. T. Chen, and F. Lombardi, "On the diagnosis of programmable interconnect systems: Theory and application," in Proceedings of the 14th VLSI Test Symposium, April 28-May 1 1996, pp. 204-209.
-
(1996)
Proceedings of the 14th VLSI Test Symposium
, pp. 204-209
-
-
Huang, W.K.1
Chen, X.T.2
Lombardi, F.3
-
13
-
-
0033316858
-
Minimizing the number of programming steps for diagnosis of interconnect faults in FPGAs
-
Shanghai, China, Nov.
-
Y. Yu, J. Xu, W. K. Huang, and F. Lombardi, "Minimizing the number of programming steps for diagnosis of interconnect faults in FPGAs," in Proceedings of the 8th Asian Test Symposium, Shanghai, China, Nov. 1999, pp. 357-362.
-
(1999)
Proceedings of the 8th Asian Test Symposium
, pp. 357-362
-
-
Yu, Y.1
Xu, J.2
Huang, W.K.3
Lombardi, F.4
-
14
-
-
0029490526
-
A row-based FPGA for single and multiple stuck-at fault detection
-
Lafayette, LA, November 13-15
-
X. Chen, W. Huang, F. Lombardi, and X. Sun, "A row-based FPGA for single and multiple stuck-at fault detection," in Proceedings of the IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems, Lafayette, LA, November 13-15 1995, pp. 225-233.
-
(1995)
Proceedings of the IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems
, pp. 225-233
-
-
Chen, X.1
Huang, W.2
Lombardi, F.3
Sun, X.4
-
15
-
-
0033322016
-
A CMOS-based logic cell for the implementation of self-checking FPGAs
-
Albuquerque, NM, USA, November 1-3
-
P. Lala, A. Singh, and A. Walker, "A CMOS-based logic cell for the implementation of self-checking FPGAs," in Proceedings of the International Symposium on Defect and Fault Tolerance in VLSI Systems, Albuquerque, NM, USA, November 1-3 1999, pp. 238-246.
-
(1999)
Proceedings of the International Symposium on Defect and Fault Tolerance in VLSI Systems
, pp. 238-246
-
-
Lala, P.1
Singh, A.2
Walker, A.3
-
16
-
-
0032096706
-
Low over-head fault-tolerant FPGA systems
-
June
-
J. Lach, W. H. Mangione-Smith, and M. Potkonjak, "Low over-head fault-tolerant FPGA systems," IEEE Transactions on Very Large Scale Integrated (VLSI) Systems, vol. 6, no. 2, pp. 212-221, June 1998.
-
(1998)
IEEE Transactions on Very Large Scale Integrated (VLSI) Systems
, vol.6
, Issue.2
, pp. 212-221
-
-
Lach, J.1
Mangione-Smith, W.H.2
Potkonjak, M.3
-
17
-
-
84889958959
-
Dynamic fault tolerance in FPGAs via partial reconfiguration
-
Napa Valley, CA, Apr.
-
J. Emmert, C. Stroud, B. Skaggs, and M. Abramovici, "Dynamic fault tolerance in FPGAs via partial reconfiguration," in Proceedings of the IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM 2000), Napa Valley, CA, Apr. 2000, pp. 165-174.
-
(2000)
Proceedings of the IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM 2000)
, pp. 165-174
-
-
Emmert, J.1
Stroud, C.2
Skaggs, B.3
Abramovici, M.4
-
18
-
-
84949757980
-
Tunable fault tolerance for runtime reconfigurable architectures
-
Napa Valley, CA, Apr.
-
S. K. Sinha, P. M. Karmachik, and S. C. Goldstein, "Tunable fault tolerance for runtime reconfigurable architectures," in Proceedings of the IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM 2000), Napa Valley, CA, Apr. 2000, pp. 185-192.
-
(2000)
Proceedings of the IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM 2000)
, pp. 185-192
-
-
Sinha, S.K.1
Karmachik, P.M.2
Goldstein, S.C.3
-
19
-
-
0031362699
-
Defect tolerance on the Teramac custom computer
-
Napa Valley, CA, April 16-18
-
B. Culbertson, R. Amerson, R. Carter, P. Kuekes, and G. Snider, "Defect tolerance on the Teramac custom computer," in Proceedings of the 1997 IEEE Symposium on FPGA'sfor Custom Computing Machines (FCCM '97), Napa Valley, CA, April 16-18 1997.
-
(1997)
Proceedings of the 1997 IEEE Symposium on FPGA'sfor Custom Computing Machines (FCCM '97)
-
-
Culbertson, B.1
Amerson, R.2
Carter, R.3
Kuekes, P.4
Snider, G.5
-
20
-
-
0032510985
-
A defect-tolerant computer architecture: Opportunities for nanotechnology
-
12 June
-
J. R. Heath, P. J. Kuekes, G. S. Snider, and R. S. Williams, "A defect-tolerant computer architecture: Opportunities for nanotechnology," Science, vol. 280, pp. 1716-1721, 12 June 1998.
-
(1998)
Science
, vol.280
, pp. 1716-1721
-
-
Heath, J.R.1
Kuekes, P.J.2
Snider, G.S.3
Williams, R.S.4
-
21
-
-
0003391890
-
Combinatorial Group Testing and Its Applications, 2nd ed.
-
F. Hwang, Ed. New York: World Scientific
-
D.-Z. Du and F. K. Hwang, Combinatorial Group Testing and its Applications, 2nd ed., ser. Series on Applied Mathematics, F. Hwang, Ed. New York: World Scientific, 2000, vol. 12.
-
(2000)
Ser. Series on Applied Mathematics
, vol.12
-
-
Du, D.-Z.1
Hwang, F.K.2
-
22
-
-
0001243071
-
The detection of defective members of large populations
-
Dec.
-
R. Dorfman, "The detection of defective members of large populations," Annals of Mathematical Statistics, vol. 14, pp. 436-440, Dec. 1943.
-
(1943)
Annals of Mathematical Statistics
, vol.14
, pp. 436-440
-
-
Dorfman, R.1
-
23
-
-
0022037454
-
Born again group testing: Multiaccess communications
-
Mar.
-
J. K. Wolf, "Born again group testing: Multiaccess communications," IEEE Transactions on Information Theory, vol. IT-31, no. 2, pp. 185-191, Mar. 1985.
-
(1985)
IEEE Transactions on Information Theory
, vol.IT-31
, Issue.2
, pp. 185-191
-
-
Wolf, J.K.1
-
24
-
-
0142194963
-
Non-adaptive group testing in the presence of errors
-
Los Alamos National Laboratory, Los Alamos, NM, Sept
-
E. Knill, W. J. Bruno, and D. C. Torney, "Non-adaptive group testing in the presence of errors," Los Alamos National Laboratory, Los Alamos, NM, Tech. Rep. LAUR-95-2040, Sept, 1996.
-
(1996)
Tech. Rep.
, vol.LAUR-95-2040
-
-
Knill, E.1
Bruno, W.J.2
Torney, D.C.3
-
26
-
-
0039830178
-
Developments in "The synthesis of reliable organisms from unreliable components"
-
N. Pippenger, "Developments in "The synthesis of reliable organisms from unreliable components"," Proceedings of Symposia in Pure Mathematics, vol. 50, pp. 311-324, 1990.
-
(1990)
Proceedings of Symposia in Pure Mathematics
, vol.50
, pp. 311-324
-
-
Pippenger, N.1
-
27
-
-
0030386114
-
Highly fault-tolerant parallel computation
-
Burlington, VA, USA, Oct. 14-16
-
D. A. Spielman, "Highly fault-tolerant parallel computation," in Proceedings of the 37th Annual IEEE Conference on Foundations of Computer Science (FOCS'96), Burlington, VA, USA, Oct. 14-16 1996, pp. 154-163.
-
(1996)
Proceedings of the 37th Annual IEEE Conference on Foundations of Computer Science (FOCS'96)
, pp. 154-163
-
-
Spielman, D.A.1
-
28
-
-
0025462762
-
The analysis of one-dimensional linear cellular automata and their aliasing properties
-
July
-
M. Serra, T. Slater, J. C. Munzio, and D. M. Miller, "The analysis of one-dimensional linear cellular automata and their aliasing properties, " IEEE Transactions on Computer Aided Design, vol. 9, no. 7, pp. 767-778, July 1990.
-
(1990)
IEEE Transactions on Computer Aided Design
, vol.9
, Issue.7
, pp. 767-778
-
-
Serra, M.1
Slater, T.2
Munzio, J.C.3
Miller, D.M.4
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