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Volumn , Issue , 2005, Pages 381-386
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System level power and performance modeling of GALS point-to-point communication interfaces
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Author keywords
Globally asynchronous locally synchronous; Mixed clock FIFO; Pausible clock
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Indexed keywords
MICROPROCESSOR CHIPS;
PERFORMANCE;
POWER CONTROL;
POWER ELECTRONICS;
GLOBALLY ASYNCHRONOUS LOCALLY SYNCHRONOUS (GALS);
MIXED CLOCK FIFO;
PAUSIBLE CLOCK;
TELECOMMUNICATION SYSTEMS;
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EID: 28444449170
PISSN: 15334678
EISSN: None
Source Type: Conference Proceeding
DOI: 10.1109/lpe.2005.195551 Document Type: Conference Paper |
Times cited : (10)
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References (12)
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