Array-based architecture for FET-based, nanoscale electronics

IEEE Transactions on Nanotechnology

Volumn 2, Issue 1, 2003, Pages 23-32

  DeHon, André ^a  

^a CALIFORNIA INSTITUTE OF TECHNOLOGY   (United States)

Author keywords

Bootstrapping; Electronic nanotechnology; Molecular electronics; Nanoscale FET logic; Programmable architecture

Indexed keywords

CARBON NANOTUBES; CRYSTAL DEFECTS; FIELD PROGRAMMABLE GATE ARRAYS; LOGIC GATES; NANOTECHNOLOGY; STATIC RANDOM ACCESS STORAGE; VLSI CIRCUITS;

BOOTSTRAPPING; ELECTRONIC NANOTECHNOLOGY; MOLECULAR ELECTRONICS; PROGRAMMABLE ARCHITECTURE;

FIELD EFFECT TRANSISTORS;

EID: 0141499770     PISSN: 1536125X     EISSN: None     Source Type: Journal    
DOI: 10.1109/TNANO.2003.808508     Document Type: Article

References (24)

1. C. Dekker, "Carbon nanotubes as molecular quantum wires," Phys. Today, pp. 22-28, May 1999.
2. Y. Huang, X. Duan, Q. Wei, and C. M. Lieber, "Directed assemble of one-dimensional nanostructures into functional networks," Science, vol. 291, pp. 630-633, Jan. 2001.
3. Y. Cui, L. J. Lauhon, M. S. Gudiksen, J. Wang, and C. M. Lieber, "Diameter-controlled synthesis of single crystal silicon nanowires," Appl. Phys. Lett., vol. 78, no. 15, pp. 2214-2216, 2001.
4. A. M. Morales and C. M. Lieber, "A laser ablation method for synthesis of crystalline semiconductor nanowires," Science, vol. 279, pp. 208-211, 1998.
5. Y. Chen, D. A. A. Ohlberg, G. Medeiros-Ribeiro, Y. A. Chang, and R. S. Williams, "Self-assembled growth of epitaxial erbium disilicide nanowires on silicon (001)," Appl. Phys. Lett., vol. 76, no. 26, pp. 4004-4006, 2000.
6. Y. Cui, X. Duan, J. Hu, and C. M. Lieber, "Doping and electrical transport in silicon nanowires," J. Phys. Chem. B, vol. 104, no. 22, pp. 5213-5216, June 8, 2000.
7. T. Rueckes, K. Kim, E. Joselevich, G. Y. Tseng, C.-L. Cheung, and C. M. Lieber, "Carbon nanotube based nonvolatile random access memory for molecular computing," Science, vol. 289, pp. 94-97, 2000.
8. Y. Huang, X. Duan, Y. Cui, L. Lauhon, K. Kim, and C. M. Lieber, "Logic gates and computation from assembled nanowire building blocks," Science, vol. 294, pp. 1313-1317, 2001.
9. S. J. Trans, A. R. M. Verschueren, and C. Dekker, "Room-temperature transistor based on a single carbon nanotube," Nature, vol. 393, pp. 49-51, May 7, 1998.
10. V. Derycke, R. Martel, J. Appenzeller, and Ph. Avouris, "Carbon nanotube inter- and intramolecular logic gates," Nano Lett., vol. 1, no. 9, pp. 453-456, 2001.
11. S. J. Wind, J. Appenzeller, R. Martel, V. Deycke, and Ph. Avouris, "Vertical scaling a of carbon nanotube field-effect transistors using top gate electrodes," Appl. Phys. Lett., vol. 80, no. 20, pp. 3817-3819, 2002.
12. C. P. Collier, E. W. Wong, M. Belohradsky, F. M. Raymo, J. F. Stoddard, P. J. Kuekes, R. S. Williams, and J. R. Heath, "Electronically configurable molecular-based logic gates," Science, vol. 285, pp. 391-394, 1999.
13. J. Rose, R. Francis, D. Lewis, and P. Chow, "Architecture of field-programmable gate arrays: The effect of logic block functionality on area efficiency," IEEE J. Solid-State Circuits, vol. 25, no. 5, pp. 1217-1225, Oct. 1990.
14. J. Kouloheris and A. El Gamal, "Pla-based FPGA area versus cell granularity," in Proc. IEEE Custom Integrated Circuits Conf., Boston, MA, May 1992, pp. 4.3.1-4.3.4.
15. A. DeHon, "Reconfigurable architectures for general-purpose computing," MIT Artif. Intell. Lab., Cambridge, MA, AI Tech. Rep. 1586, Oct. 1996.
16. J. R. Heath, P. J. Kuekes, G. S. Snider, and R. S. Williams, "A defect-tolerant computer architecture: Opportunities for nanotechnology," Science, vol. 280, pp. 1716-1721, June 12, 1998.
17. S. C. Goldstein and M. Budiu, "Nanofabrics: Spatial computing using molecular electronics," in Proc. 28th Annu. Int. Symp. Computer Architecture, Gotenbörg, Sweden, June 2001, pp. 178-189.
18. C. M. Lieber and X. Duan, "Nanofet threshold voltages," unpublished, Dec. 2001.
19. S. Y. Chou, P. R. Krauss, W. Zhang, L. Guo, and L. Zhuang, "Sub-10 nm imprint lithography and applications," J. Vacuum Sci. Technol. B, vol. 15, no. 6, pp. 2897-2904, Nov./Dec. 1997.
20. S. Williams and P. Kuekes, "Demultiplexer for a molecular wire crossbar network," U.S. Patent 6256767, July 3, 2001.
21. V. J. Coli, "Introduction to programmable array logic," BYTE, pp. 207-219, Jan. 1987.
22. Monolithic Memories, Inc., PAL Handbook, 3rd ed. Santa Clara, CA: Monolithic Memories, Incorporated, 1983.
23. (2001) International technology roadmap for semiconductors. [Online]. Available: http://public.itrs.net/Files/2001ITRS/
24. M. S. Gudiksen, J. Wang, and C. M. Lieber, "Synthetic control of the diameter and length of semiconductor nanowires," J. Phys. Chem. B, vol. 105, pp. 4062-4064, 2001.