Why area might reduce power in nanoscale CMOS

Proceedings - IEEE International Symposium on Circuits and Systems

Volumn , Issue , 2005, Pages 2329-2332

  Beckett, Paul ^a   Goldstein, Seth Copen ^b  

^a RMIT UNIVERSITY   (Australia)

^b Carnegie Mellon University   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

AREA-PROPORTIONAL; GATE LEAKAGES; NANOSCALE CMOS; NANOSCALE TECHNOLOGIES; POWER-LOSSES; SCALING REGIMES; SHORT-CIRCUIT POWER; SPATIAL COMPUTING; SUBTHRESHOLD;

NANOSTRUCTURED MATERIALS;

EID: 67649107515     PISSN: 02714310     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISCAS.2005.1465091     Document Type: Conference Paper

References (26)

1. S. C. Goldstein and M. Budiu, "Nanofabrics: Spatial computing using molecular electronics," in Proc. 28th Int'l Symposium on Computer Architecture, Goteborg, Sweden, 2001, pp. 178-189.
2. C. D. Thompson, "Area-time complexity for vlsi," in Proc. Eleventh Annual ACM Symposium on Theory of Computing, 1979, pp. 81-88.
3. H. Abelson and P. Andreae, "Information transfer and area-time tradeoffs for vlsi multiplication," Communications of the ACM, vol. 23, no. 1, pp. 20-23, 1980.
4. R. J. Lipton and R. Sedgewick, "Lower bounds for vlsi," in Proc. Thirteenth Annual ACM Symposium on Theory of Computing, 1981, pp. 300-307.
5. R. P. Brent and H. T. Kung, "The chip complexity of binary arithmetic," in Proc. Twelfth Annual ACM Symposium on Theory of Computing, Los Angeles, CA, USA, 1980, pp. 190-200.
6. -, "The area-time complexity of binary multiplication," Journal of the ACM, vol. 28, no. 3, pp. 521-534, 1981.
7. I. E. Sutherland, "Micropipelines," Communications of the ACM, vol. 32, no. 6, pp. 720-738, 1989.
8. D. Lee, W. Kwong, D. Blaauw, and D. Sylvester, "Analysis and minimization techniques for total leakage considering gate oxide leakage," in Proc. 40th Conference on Design Automation, 2003, pp. 175-180.
9. D. J. Frank, R. H. Dennard, E. Nowak, P. M. Solomon, Y. Taur, and H.-S. P. Wong, "Device scaling limits of si mosfets and their application dependencies," Procs. of the IEEE, vol. 89, no. 3, pp. 259-288, 2001.
10. P. K. Ko, J. Huang, Z. Liu, and C. Hu, "Bsim3 for analog and digital circuit simulation," in Proc. IEEE Symposium on VLSI Technology CAD, 1993, pp. 400-429.
11. SIA, Int'l Technology Roadmap for Semiconductors-2003 update, 2003.
12. K. Chen, C. Hu, P. Fang, M. R. Lin, and D. L. Wollesen, "Predicting cmos speed with gate oxide and voltage scaling and interconnect loading effects," IEEE Trans. on Electron Devices, vol. 44, no. 11, pp. 1951-1957, 1997.
13. M. J. Flynn, P. Hung, and K. W. Rudd, "Deep-submicron microprocessor design issues," IEEE Micro, vol. 19, pp. 11-22, 1999.
14. P. Zarkesh-Ha, J. A. Davis, W. Loh, and J. D. Meindl, "Prediction of interconnect fan-out distribution using rent's rule," in Proc. Int'l Workshop on System-level Interconnect Prediction (SLIP00), 2000, pp. 107-112.
15. H. J. M. Veendrick, "Short-circuit dissipation of static cmos circuitry and its impact on the design of buffer circuits," IEEE Journal of Solid-State Circuits, vol. 19, no. 4, pp. 468-473, 1984.
16. R. Ball, "Smaller processes lead to fpga leakage crisis," Electronics Weekly, vol. September 30, 2003. [Online]. Available: http://www.reedelectronics. com/electronicnews/article/CA332188
17. C. K. Huang and N. Goldsman, "Modeling the limits of gate oxide scaling with a schrodinger-based method of direct tunneling gate currents of nanoscale mosfets," in Proc. 1st IEEE Conference on Nanotechnology. IEEE-NANO 2001, 2001, pp. 335-339.
18. K. Roy, S. Mukhopadhyay, and H. Mahmoodi-Meimand, "Leakage current mechanisms and leakage reduction techniques in deepsubmicrometer cmos circuits," Proc. of the IEEE, vol. 91, no. 2, pp. 305-327, Feb. 2003.
19. S. Keeney, R. Bez, D. Cantarelli, F. Piccinini, A. Mathewson, L. Ravazzi, and C. Lombardi, "Complete transient simulation of flash eeprom devices," IEEE Trans. on Electron Devices, vol. 39, no. 12, pp. 2750-2757, 1992.
20. Y. C. Yeo, Q. Lu, W. C. Lee, T. J. King, C. Hu, X. Wang, X. Guo, and T. P. Ma, "Direct tunneling gate leakage current in transistors with ultrathin silicon nitride gate dielectric," IEEE Electron Device Letters, vol. 21, no. 11, pp. 540-542, 2000.
21. H.-S. P. Wong, D. J. Frank, P. M. Solomon, C. H. J. Wann, and J. J. Welser, "Nanoscale cmos," Proc. of the IEEE, vol. 87, no. 4, pp. 537-70, 1999.
22. Y. C. Yeo, T. J. King, and C. Hu, "Direct tunneling leakage current and scalability of alternative gate dielectrics," Applied Physics Letters, vol. 81, no. 11, pp. 2091-2093, 2002.
23. J. Kedzierski, E. Nowak, T. Kanarsky, Y. Zhang, D. Boyd, R. Carruthers, C. Cabral, R. Amos, C. Lavoie, R. Roy, J. Newbury, E. Sullivan, J. Benedict, P. Saunders, K. Wong, D. Canaperi, M. Krishnan, K.-L. Lee, B. A. Rainey, D. Fried, P. Cottrell, H.-S. P. Wong, M. Ieong, and W. Haensch, "Metal-gate finfet and fully-depleted soi devices using total gate silicidation," in Proc. Int'l Electron Devices Meeting, IEDM '02, 2002, pp. 247-250.
24. P. Beckett, "Exploiting multiple functionality for nano-scale reconfigurable systems," in Proc. 10th Reconfigurable Architectures Workshop, RAW2003, 2003, pp. 50-55.
25. Y. Naveh and K. K. Likharev, "Modeling of 10-nm scale ballistic mosfet's," IEEE Electron Device Letters, vol. 21, no. 5, pp. 242-244, 2000.
26. M. M. Ziegler and M. R. Stan, "A case for cmos/nano co-design," in Proc. Int'l Symposium on Circuits and Systems, ISCAS'02, 2002, pp. 348-352.