-
1
-
-
32044469534
-
-
http://www.futuremark.com/products/3dmark05, 2006.
-
(2006)
-
-
-
2
-
-
0037331006
-
"Simulating a $2M Commercial Server on a $2K PC"
-
Feb
-
A. Alameldeen, M. Martin, C. Mauer, K. Moore, M. Xu, D. Sorin, M. Hill, and D. Wood, "Simulating a $2M Commercial Server on a $2K PC," Computer, vol. 36, no. 2, pp. 50-57, Feb. 2003.
-
(2003)
Computer
, vol.36
, Issue.2
, pp. 50-57
-
-
Alameldeen, A.1
Martin, M.2
Mauer, C.3
Moore, K.4
Xu, M.5
Sorin, D.6
Hill, M.7
Wood, D.8
-
4
-
-
33744484309
-
"BioBench: A Benchmark Suite of Bioinformatics Applications"
-
K. Albayraktaroglu, A. Jaleel, X. Wu, M. Franklin, B. Jacob, C. Tseng, and D. Yeung, "BioBench: A Benchmark Suite of Bioinformatics Applications," Proc. Int'l Symp. Performance Analysis of Systems and Software, 2005.
-
(2005)
Proc. Int'l Symp. Performance Analysis of Systems and Software
-
-
Albayraktaroglu, K.1
Jaleel, A.2
Wu, X.3
Franklin, M.4
Jacob, B.5
Tseng, C.6
Yeung, D.7
-
5
-
-
32044439738
-
-
http://www.llnl.gov/asci_benchmarks/asci/asci_code_list.html, 2006.
-
(2006)
-
-
-
6
-
-
0036469652
-
"SimpleScalar: An Infrastructure for Computer System Modeling"
-
Feb
-
T. Austin, E. Larson, and D. Ernst, "SimpleScalar: An Infrastructure for Computer System Modeling," Computer, vol. 35, no. 2, pp. 59-67, Feb. 2002.
-
(2002)
Computer
, vol.35
, Issue.2
, pp. 59-67
-
-
Austin, T.1
Larson, E.2
Ernst, D.3
-
7
-
-
33744497844
-
"Accelerating Multiprocessor Simulation with a Memory Timestamp Record"
-
K. Barr, H. Pan, M. Zhang, and K. Asanovic, "Accelerating Multiprocessor Simulation with a Memory Timestamp Record," Proc. Int'l Symp. Performance Analysis of Systems and Software, 2005.
-
(2005)
Proc. Int'l Symp. Performance Analysis of Systems and Software
-
-
Barr, K.1
Pan, H.2
Zhang, M.3
Asanovic, K.4
-
9
-
-
0032069891
-
"Calibration of Microprocessor Performance Models"
-
May
-
B. Black and J. Shen, "Calibration of Microprocessor Performance Models," Computer, vol. 31, no. 5, pp. 59-65, May 1998.
-
(1998)
Computer
, vol.31
, Issue.5
, pp. 59-65
-
-
Black, B.1
Shen, J.2
-
10
-
-
0032070245
-
"Performance Analysis and Its Impact on Design"
-
May
-
P. Bose and T. Conte, "Performance Analysis and Its Impact on Design," Computer, vol. 31, no. 5, pp. 41-49, May 1998.
-
(1998)
Computer
, vol.31
, Issue.5
, pp. 41-49
-
-
Bose, P.1
Conte, T.2
-
11
-
-
0032658099
-
"Challenges in Processor Modeling and Validation"
-
May/June
-
P. Bose, T. Conte, and T. Austin, "Challenges in Processor Modeling and Validation," IEEE Micro, vol. 19, no. 3, May/June 1999.
-
(1999)
IEEE Micro
, vol.19
, Issue.3
-
-
Bose, P.1
Conte, T.2
Austin, T.3
-
13
-
-
0346898058
-
"New Methodology for Early-Stage, Microarchitecture-Level Power-Performance Analysis of Microprocessors"
-
Sept
-
D. Brooks, P. Bose, V. Srinivasan, M. Gschwind, P. Emma, and M. Rosenfield, "New Methodology for Early-Stage, Microarchitecture-Level Power-Performance Analysis of Microprocessors," IBM J. Research and Development, vol. 47, nos. 5/6, pp. 653-670, Sept. 2003.
-
(2003)
IBM J. Research and Development
, vol.47
, Issue.5-6
, pp. 653-670
-
-
Brooks, D.1
Bose, P.2
Srinivasan, V.3
Gschwind, M.4
Emma, P.5
Rosenfield, M.6
-
14
-
-
0005369980
-
"Precise and Accurate Processor Simulation"
-
H. Cain, K. Lepak, B. Schwartz, and M. Lipasti, "Precise and Accurate Processor Simulation," Proc. Workshop Computer Architecture Evaluation Using Commercial Workloads, 2002.
-
(2002)
Proc. Workshop Computer Architecture Evaluation Using Commercial Workloads
-
-
Cain, H.1
Lepak, K.2
Schwartz, B.3
Lipasti, M.4
-
16
-
-
32044444213
-
"Direct SMARTS: Accelerating Microarchitectural Simulation through Direct Execution"
-
master's thesis, Carnegie Mellon Univ
-
S. Chen, "Direct SMARTS: Accelerating Microarchitectural Simulation through Direct Execution," master's thesis, Carnegie Mellon Univ., 2004.
-
(2004)
-
-
Chen, S.1
-
17
-
-
4243073044
-
"Parallel Simulation of Chip-Multiprocessor Architectures"
-
July
-
M. Chidester and A. George, "Parallel Simulation of Chip-Multiprocessor Architectures," ACM Trans. Modeling and Computer Simulation, vol. 12, no. 3, pp. 176-200, July 2002.
-
(2002)
ACM Trans. Modeling and Computer Simulation
, vol.12
, Issue.3
, pp. 176-200
-
-
Chidester, M.1
George, A.2
-
18
-
-
0038008203
-
"MisSPECulation: Partial and Misleading Use of SPEC CPU2000 in Computer Architecture Conferences"
-
Panel Discussion at Int'l Symp. Computer Architecture
-
D. Citron, "MisSPECulation: Partial and Misleading Use of SPEC CPU2000 in Computer Architecture Conferences," Panel Discussion at Int'l Symp. Computer Architecture, 2003.
-
(2003)
-
-
Citron, D.1
-
20
-
-
1842860791
-
"Combining Trace Sampling with Single Pass Methods for Efficient Cache Simulation"
-
June
-
T. Conte, M. Hirsch, and W. Hwu, "Combining Trace Sampling with Single Pass Methods for Efficient Cache Simulation," IEEE Trans. Computers, vol. 47, no. 6, pp. 714-720, June 1998.
-
(1998)
IEEE Trans. Computers
, vol.47
, Issue.6
, pp. 714-720
-
-
Conte, T.1
Hirsch, M.2
Hwu, W.3
-
25
-
-
32044469521
-
"Errata On: Measuring Experimental Error in Microprocessor Simulation"
-
Mar
-
R. Desikan, D. Burger, S. Keckler, L. Cruz, F. Latorre, A. González, and M. Valero, "Errata On: Measuring Experimental Error in Microprocessor Simulation," Computer Architecture News, vol. 30, no. 1, Mar. 2002.
-
(2002)
Computer Architecture News
, vol.30
, Issue.1
-
-
Desikan, R.1
Burger, D.2
Keckler, S.3
Cruz, L.4
Latorre, F.5
González, A.6
Valero, M.7
-
29
-
-
0037325558
-
"Designing Computer Architecture Workloads"
-
Feb
-
L. Eeckhout, H. Vandierendonck, and K. De Bosschere, "Designing Computer Architecture Workloads," Computer, vol. 36, no. 2, pp. 65-71, Feb. 2003.
-
(2003)
Computer
, vol.36
, Issue.2
, pp. 65-71
-
-
Eeckhout, L.1
Vandierendonck, H.2
De Bosschere, K.3
-
30
-
-
1842860792
-
"Accurately Warmed-Up Trace Samples for the Evaluation of Cache Memories"
-
L. Eeckhout, S. Eyerman, B. Callens, and K. De Bosschere, "Accurately Warmed-Up Trace Samples for the Evaluation of Cache Memories," Proc. High Performance Computing Symp., 2003.
-
(2003)
Proc. High Performance Computing Symp.
-
-
Eeckhout, L.1
Eyerman, S.2
Callens, B.3
De Bosschere, K.4
-
31
-
-
1842852992
-
"Efficient Simulation of Trace Samples on Parallel Machines"
-
Mar
-
L. Eeckhout and K. De Bosschere, "Efficient Simulation of Trace Samples on Parallel Machines," Parallel Computing, vol. 30, no. 3, pp. 317-335, Mar. 2004.
-
(2004)
Parallel Computing
, vol.30
, Issue.3
, pp. 317-335
-
-
Eeckhout, L.1
De Bosschere, K.2
-
32
-
-
11844256347
-
"Speeding Up Architectural Simulations for High Performance Processors"
-
L. Eeckhout and K. De Bosschere, "Speeding Up Architectural Simulations for High Performance Processors," SIMULATION: Trans. Soc. Modeling and Simulation Int'l, vol. 80, no. 9, pp. 451-468, 2004.
-
(2004)
SIMULATION: Trans. Soc. Modeling and Simulation Int'l
, vol.80
, Issue.9
, pp. 451-468
-
-
Eeckhout, L.1
De Bosschere, K.2
-
33
-
-
32044439227
-
-
http://www.eembc.org, 2006.
-
(2006)
-
-
-
35
-
-
0036470119
-
"Asim: A Performance Model Framework"
-
Feb
-
J. Emer, P. Ahuja, E. Borch, A. Klauser, C. Luk, S. Manne, S. Mukherjee, H. Patil, S. Wallace, N. Binkert, R. Espasa, and T. Juan, "Asim: A Performance Model Framework," Computer, vol. 35, no. 2, pp. 68-76, Feb. 2002.
-
(2002)
Computer
, vol.35
, Issue.2
, pp. 68-76
-
-
Emer, J.1
Ahuja, P.2
Borch, E.3
Klauser, A.4
Luk, C.5
Manne, S.6
Mukherjee, S.7
Patil, H.8
Wallace, S.9
Binkert, N.10
Espasa, R.11
Juan, T.12
-
36
-
-
0030712794
-
"Modeling Cost/Performance of a Parallel Computer Simulator"
-
Jan
-
B. Falsafi and D. Wood, "Modeling Cost/Performance of a Parallel Computer Simulator," ACM Trans. Modeling and Computer Simulation, vol. 7, no. 1, pp. 104-130, Jan. 1997.
-
(1997)
ACM Trans. Modeling and Computer Simulation
, vol.7
, Issue.1
, pp. 104-130
-
-
Falsafi, B.1
Wood, D.2
-
37
-
-
32044473180
-
-
http://www.cs.wisc.edu/gems, 2006.
-
(2006)
-
-
-
38
-
-
0034442186
-
"FLASH vs. (Simulated) FLASH: Closing the Simulation Loop"
-
J. Gibson, R. Kunz, D. Ofelt, M. Horowitz, J. Hennessy, and M. Heinrich, "FLASH vs. (Simulated) FLASH: Closing the Simulation Loop," Proc. Int'l Conf. Architectural Support for Programming Languages and Operating Systems, 2000.
-
(2000)
Proc. Int'l Conf. Architectural Support for Programming Languages and Operating Systems
-
-
Gibson, J.1
Kunz, R.2
Ofelt, D.3
Horowitz, M.4
Hennessy, J.5
Heinrich, M.6
-
39
-
-
33645440894
-
"DiST A Simple, Reliable, and Scalable Method to Significantly Reduce Processor Architecture Simulation Time"
-
S. Girbal, G. Mouchard, A. Cohen, and O. Temam, "DiST A Simple, Reliable, and Scalable Method to Significantly Reduce Processor Architecture Simulation Time," Proc. Joint Int'l Conf. Measurement and Modeling of Computer Systems, 2003.
-
(2003)
Proc. Joint Int'l Conf. Measurement and Modeling of Computer Systems
-
-
Girbal, S.1
Mouchard, G.2
Cohen, A.3
Temam, O.4
-
40
-
-
12344269377
-
"Analysis of Simulation-Adapted SPEC 2000 Benchmarks"
-
Sept
-
I. Gómez, L. Pifiuel, M. Prieto, and F. Tirado, "Analysis of Simulation-Adapted SPEC 2000 Benchmarks," Computer Architecture News, vol. 30, no. 4, pp. 4-10, Sept. 2002.
-
(2002)
Computer Architecture News
, vol.30
, Issue.4
, pp. 4-10
-
-
Gómez, I.1
Pifiuel, L.2
Prieto, M.3
Tirado, F.4
-
42
-
-
84962779213
-
"MiBench: A Free, Commercially Representative Embedded Benchmark Suite"
-
M. Guthaus, J. Ringenberg, D. Ernst, T. Austin, T. Mudge, and R. Brown, "MiBench: A Free, Commercially Representative Embedded Benchmark Suite," Proc. Workshop Workload Characterization, 2001.
-
(2001)
Proc. Workshop Workload Characterization
-
-
Guthaus, M.1
Ringenberg, J.2
Ernst, D.3
Austin, T.4
Mudge, T.5
Brown, R.6
-
45
-
-
0034226001
-
"SPEC CPU2000: Measuring CPU Performance in the New Millennium"
-
July
-
J. Henning, "SPEC CPU2000: Measuring CPU Performance in the New Millennium," Computer, vol. 33, no. 7, pp. 28-35, July 2000.
-
(2000)
Computer
, vol.33
, Issue.7
, pp. 28-35
-
-
Henning, J.1
-
46
-
-
0036470602
-
"Rsim: Simulating Shared-Memory Multiprocessors with ILP Processors"
-
Feb
-
C. Hughes, V. Pai, P. Ranganathan, and S. Adve, "Rsim: Simulating Shared-Memory Multiprocessors with ILP Processors," Computer, vol. 35, no. 2, pp. 40-49, Feb. 2002.
-
(2002)
Computer
, vol.35
, Issue.2
, pp. 40-49
-
-
Hughes, C.1
Pai, V.2
Ranganathan, P.3
Adve, S.4
-
48
-
-
32044453923
-
-
http://www.epcc.ed.ac.uk/javagrande/index_1.html, 2006.
-
(2006)
-
-
-
49
-
-
32044436192
-
"Benchmarks"
-
(draft) L. Kurian John and L. Eeckhout, eds., CRC Press, to be published
-
L. Kurian John, "Benchmarks," (draft) Modern Simulation and Analysis Techniques, L. Kurian John and L. Eeckhout, eds., CRC Press, to be published.
-
Modern Simulation and Analysis Techniques
-
-
Kurian John, L.1
-
50
-
-
32044470381
-
"Performance Modeling and Measurement Techniques"
-
(draft) L. Kurian John and L. Eeckhout, eds., CRC Press, to be published
-
L. Kurian John, "Performance Modeling and Measurement Techniques," (draft) Modern Simulation and Analysis Techniques, L. Kurian John and L. Eeckhout, eds., CRC Press, to be published.
-
Modern Simulation and Analysis Techniques
-
-
Kurian John, L.1
-
51
-
-
0028445155
-
"A Comparison of Trace-Sampling Techniques for Multi-Megabyte Caches"
-
June
-
R. Kessler, M. Hill, and D. Wood, "A Comparison of Trace-Sampling Techniques for Multi-Megabyte Caches," IEEE Trans. Computers, vol. 43, no. 6, pp. 664-675, June 1994.
-
(1994)
IEEE Trans. Computers
, vol.43
, Issue.6
, pp. 664-675
-
-
Kessler, R.1
Hill, M.2
Wood, D.3
-
52
-
-
0034317861
-
"Validating Tract-Driven Microarchitectural Simulations"
-
Nov./Dec
-
H. Khalid, "Validating Tract-Driven Microarchitectural Simulations," IEEE Micro, vol. 20, no. 6, pp. 76-82, Nov./Dec. 2000.
-
(2000)
IEEE Micro
, vol.20
, Issue.6
, pp. 76-82
-
-
Khalid, H.1
-
53
-
-
85008031236
-
"MinneSPEC: A New SPEC Benchmark Workload for Simulation-Based Computer Architecture Research"
-
June
-
A. KleinOsowski and D. Lilja, "MinneSPEC: A New SPEC Benchmark Workload for Simulation-Based Computer Architecture Research," Computer Architecture Letters, vol. 1, June 2002.
-
(2002)
Computer Architecture Letters
, vol.1
-
-
KleinOsowski, A.1
Lilja, D.2
-
55
-
-
1842849819
-
"Choosing Representative Slices of Program Execution for Microarchitecture Simulations: A Preliminary Application to the Data Stream"
-
T. Lafage and A. Seznec, "Choosing Representative Slices of Program Execution for Microarchitecture Simulations: A Preliminary Application to the Data Stream," Proc. Workshop Workload Characterization, 2000.
-
(2000)
Proc. Workshop Workload Characterization
-
-
Lafage, T.1
Seznec, A.2
-
56
-
-
0024107186
-
"Accurate Low-Cost Methods for Performance Evaluation of Cache Memory Systems"
-
Nov
-
S. Laha, J. Patel, and R. Iyer, "Accurate Low-Cost Methods for Performance Evaluation of Cache Memory Systems," IEEE Trans. Computers, vol. 37, no. 11, pp. 1325-1336, Nov. 1988.
-
(1988)
IEEE Trans. Computers
, vol.37
, Issue.11
, pp. 1325-1336
-
-
Laha, S.1
Patel, J.2
Iyer, R.3
-
59
-
-
33744504206
-
"Motivation for Variable Length Intervals and Hierarchical Phase Behavior"
-
J. Lau, E. Perelman, G. Hamerly, T. Sherwood, and B. Calder, "Motivation for Variable Length Intervals and Hierarchical Phase Behavior," Proc. Int'l Symp. Performance Analysis of Systems and Software, 2005.
-
(2005)
Proc. Int'l Symp. Performance Analysis of Systems and Software
-
-
Lau, J.1
Perelman, E.2
Hamerly, G.3
Sherwood, T.4
Calder, B.5
-
60
-
-
1842871851
-
"Accelerating Architectural Simulation by Parallel Execution of Trace Samples"
-
Sun Microsystems Laboratory Technical Report TR-93-22
-
G. Lauterbach, "Accelerating Architectural Simulation by Parallel Execution of Trace Samples," Sun Microsystems Laboratory Technical Report TR-93-22, 1993.
-
(1993)
-
-
Lauterbach, G.1
-
61
-
-
0344119460
-
"NpBench: A Benchmark Suite for Control Plane and Data Plane Applications for Network Processors"
-
B. Lee and L. Kurian John, "NpBench: A Benchmark Suite for Control Plane and Data Plane Applications for Network Processors," Proc. Int'l Conf. Computer Design, 2003.
-
(2003)
Proc. Int'l Conf. Computer Design
-
-
Lee, B.1
Kurian John, L.2
-
64
-
-
8444250655
-
"EXPERT: Expedited Simulation Exploiting Program Behavior Repetition"
-
W. Liu and M. Huang, "EXPERT: Expedited Simulation Exploiting Program Behavior Repetition," Proc. Int'l Conf. Supercomputing, 2004.
-
(2004)
Proc. Int'l Conf. Supercomputing
-
-
Liu, W.1
Huang, M.2
-
65
-
-
32044449939
-
-
http://www.bitmover.com/lm/lmbench, 2006.
-
(2006)
-
-
-
66
-
-
85008034312
-
"Efficiently Evaluating Speedup Using Sampled Processor Simulation"
-
Sept
-
Y. Luo and L. Kurian John, "Efficiently Evaluating Speedup Using Sampled Processor Simulation," Computer Architecture Letters, vol. 3, Sept. 2004.
-
(2004)
Computer Architecture Letters
, vol.3
-
-
Luo, Y.1
Kurian John, L.2
-
68
-
-
32044446841
-
-
http://m5.eecs.umich.edu, 2006.
-
(2006)
-
-
-
69
-
-
0036469676
-
"Simics: A Full System Simulation Platform"
-
Feb
-
P. Magnusson, M. Christensson, J. Eskilson, D. Forsgren, G. Halberg, J. Hogberg, F. Larsson, A. Moestedt, and B. Werner, "Simics: A Full System Simulation Platform," Computer, vol. 35, no. 2, pp. 50-58, Feb. 2002.
-
(2002)
Computer
, vol.35
, Issue.2
, pp. 50-58
-
-
Magnusson, P.1
Christensson, M.2
Eskilson, J.3
Forsgren, D.4
Halberg, G.5
Hogberg, J.6
Larsson, F.7
Moestedt, A.8
Werner, B.9
-
70
-
-
0003792125
-
"Multiprocessor Enhancements of the SimpleScalar Tool Set"
-
Mar
-
N. Manjikian, "Multiprocessor Enhancements of the SimpleScalar Tool Set," Computer Architecture News, vol. 29, no. 1, pp. 8-15, Mar. 2001.
-
(2001)
Computer Architecture News
, vol.29
, Issue.1
, pp. 8-15
-
-
Manjikian, N.1
-
71
-
-
32044447807
-
"Multifacet's General Execution-Driven Multiprocessor Simulator (GEMS) Toolset"
-
submitted
-
M. Martin, D. Sorin, B. Beckmann, M. Marty, M. Xu, A. Alameldeen, K. Moore, M. Hill, and D. Wood, "Multifacet's General Execution-Driven Multiprocessor Simulator (GEMS) Toolset," Computer Architecture News, submitted.
-
Computer Architecture News
-
-
Martin, M.1
Sorin, D.2
Beckmann, B.3
Marty, M.4
Xu, M.5
Alameldeen, A.6
Moore, K.7
Hill, M.8
Wood, D.9
-
76
-
-
0034785241
-
"Functional Abstraction Design Space Exploration of Heterogeneous Programmable Architectures"
-
P. Mishra, N. Dutt, and A. Nicolau, "Functional Abstraction Design Space Exploration of Heterogeneous Programmable Architectures," Proc. Int'l Symp. System Synthesis, 2001.
-
(2001)
Proc. Int'l Symp. System Synthesis
-
-
Mishra, P.1
Dutt, N.2
Nicolau, A.3
-
77
-
-
32044464643
-
"Techniques for Fast Simulation of Associative Cache Directories"
-
IBM Research Report RC21038
-
M. Moudgill, "Techniques for Fast Simulation of Associative Cache Directories," IBM Research Report RC21038, 1997.
-
(1997)
-
-
Moudgill, M.1
-
78
-
-
0031650582
-
"Techniques for Implementing Fast Processor Simulators"
-
M. Moudgill, "Techniques for Implementing Fast Processor Simulators," Proc. Ann. Simulation Symp., 1998.
-
(1998)
Proc. Ann. Simulation Symp.
-
-
Moudgill, M.1
-
79
-
-
84994353124
-
"Validation of Turandot, a Fast Processor Model for Microarchitecture Exploration"
-
M. Moudgill, P. Bose, and J. Moreno, "Validation of Turandot, a Fast Processor Model for Microarchitecture Exploration," Proc. Int'l Performance, Computing, and Comm. Conf., 1999.
-
(1999)
Proc. Int'l Performance, Computing, and Comm. Conf.
-
-
Moudgill, M.1
Bose, P.2
Moreno, J.3
-
80
-
-
0034290427
-
"Fast and Portable Parallel Architecture Simulators: Wisconsin Wind Tunnel II"
-
Oct.-Dec
-
S. Murkerjee, S. Reinhardt, B. Falsafi, M. Litzkow, S. Huss-Lederman, M. Hill, J. Larus, and D. Wood, "Fast and Portable Parallel Architecture Simulators: Wisconsin Wind Tunnel II," IEEE Concurrency, vol. 8, no. 4, pp. 12-20, Oct.-Dec. 2000.
-
(2000)
IEEE Concurrency
, vol.8
, Issue.4
, pp. 12-20
-
-
Murkerjee, S.1
Reinhardt, S.2
Falsafi, B.3
Litzkow, M.4
Huss-Lederman, S.5
Hill, M.6
Larus, J.7
Wood, D.8
-
81
-
-
32044447335
-
-
http://www.nas.nasa.gov/Software/NPB, 2006.
-
(2006)
-
-
-
82
-
-
0030402556
-
"The Augmint Multiprocessor Simulation Toolkit for Intel x86 Architectures"
-
A. Nguyen, M. Michael, A. Sharma, and J. Torrellas, "The Augmint Multiprocessor Simulation Toolkit for Intel x86 Architectures," Proc. Int'l Conf. Computer Design, 1996.
-
(1996)
Proc. Int'l Conf. Computer Design
-
-
Nguyen, A.1
Michael, M.2
Sharma, A.3
Torrellas, J.4
-
83
-
-
0030645301
-
"Accuracy and Speed-Up of Parallel Trace-Driven Architectural Simulation"
-
A. Nguyen, P. Bose, K. Ekanadham, A. Nanda, and M. Michael, "Accuracy and Speed-Up of Parallel Trace-Driven Architectural Simulation," Proc. Int'l Parallel Processing Symp., 1997.
-
(1997)
Proc. Int'l Parallel Processing Symp.
-
-
Nguyen, A.1
Bose, P.2
Ekanadham, K.3
Nanda, A.4
Michael, M.5
-
84
-
-
0032674031
-
"LISA - Machine Description Language for Cycle-Accurate Models of Programmable DSP Architectures"
-
S. Pees, A. Hoffmann, V. Zivojnovic, and H. Meyr, "LISA - Machine Description Language for Cycle-Accurate Models of Programmable DSP Architectures," Proc. Design Automation Conf., 1999.
-
(1999)
Proc. Design Automation Conf.
-
-
Pees, S.1
Hoffmann, A.2
Zivojnovic, V.3
Meyr, H.4
-
85
-
-
0043136464
-
"Optimizations for a Simulator Construction System Supporting Reusable Components"
-
D. Penry and D. August, "Optimizations for a Simulator Construction System Supporting Reusable Components," Proc. Design Automation Conf., 2003.
-
(2003)
Proc. Design Automation Conf.
-
-
Penry, D.1
August, D.2
-
88
-
-
33646503805
-
"Measuring Program Similarity: Experiments with SPEC CPU Benchmark Suites"
-
A. Phansalkar, A. Joshi, L. Eeckhout, and L. John, "Measuring Program Similarity: Experiments with SPEC CPU Benchmark Suites," Proc. Int'l Symp. Performance Analysis of Systems and Software, 2005.
-
(2005)
Proc. Int'l Symp. Performance Analysis of Systems and Software
-
-
Phansalkar, A.1
Joshi, A.2
Eeckhout, L.3
John, L.4
-
89
-
-
32044442395
-
"Execution-Driven Tools for Parallel Simulation of Parallel Architectures and Applications"
-
D. Poulsen and P. Yew, "Execution-Driven Tools for Parallel Simulation of Parallel Architectures and Applications," Proc. Supercomputing, 1993.
-
(1993)
Proc. Supercomputing
-
-
Poulsen, D.1
Yew, P.2
-
90
-
-
32044466822
-
-
http://www.eecs.umich.edu/panalyzer, 2006.
-
(2006)
-
-
-
91
-
-
32044473869
-
-
http://eda.ee.ucla.edu/PowerImpact, 2006.
-
(2006)
-
-
-
92
-
-
33744471950
-
"Intrinistic Checkpointing: A Methodology for Decreasing Simulation Time through Binary Modification"
-
J. Ringenberg, C. Pelosi, D. Oehmke, and T. Mudge, "Intrinistic Checkpointing: A Methodology for Decreasing Simulation Time through Binary Modification," Proc. Int'l Symp. Performance Analysis of Systems and Software, 2005.
-
(2005)
Proc. Int'l Symp. Performance Analysis of Systems and Software
-
-
Ringenberg, J.1
Pelosi, C.2
Oehmke, D.3
Mudge, T.4
-
93
-
-
0029512781
-
"Complete Computer Simulation: The SimOS Approach"
-
Winter
-
M. Rosenblum, S. Herrod, E. Witchel, and A. Gupta, "Complete Computer Simulation: The SimOS Approach," Parallel and Distributed Technology, vol. 3, no. 4, pp. 35-43, Winter 1995.
-
(1995)
Parallel and Distributed Technology
, vol.3
, Issue.4
, pp. 35-43
-
-
Rosenblum, M.1
Herrod, S.2
Witchel, E.3
Gupta, A.4
-
94
-
-
0030653560
-
"Using the SimOS Machine Simulator to Study Complex Computer Systems"
-
Jan
-
M. Rosenblum, E. Bugnion, S. Devine, and S. Herrod, "Using the SimOS Machine Simulator to Study Complex Computer Systems," Trans. Modeling and Computer Simulation, vol. 7, no. 1, pp. 78-103, Jan. 1997.
-
(1997)
Trans. Modeling and Computer Simulation
, vol.7
, Issue.1
, pp. 78-103
-
-
Rosenblum, M.1
Bugnion, E.2
Devine, S.3
Herrod, S.4
-
95
-
-
32044467470
-
-
http://rsim.cs.uiuc.edu/distribution, 2006.
-
(2006)
-
-
-
97
-
-
32044468837
-
-
http://math.nist.gov/scimark2, 2006.
-
(2006)
-
-
-
98
-
-
0348158498
-
"Design and Validation of a Performance and Power Simulator for PowerPC Systems"
-
Sept./Nov
-
H. Shafi, P. Bohrer, J. Phelan, C. Rusu, and J. Peterson, "Design and Validation of a Performance and Power Simulator for PowerPC Systems," IBM J. Research and Development, vol. 47, nos. 5/6, pp. 641-651, Sept./Nov. 2003.
-
(2003)
IBM J. Research and Development
, vol.47
, Issue.5-6
, pp. 641-651
-
-
Shafi, H.1
Bohrer, P.2
Phelan, J.3
Rusu, C.4
Peterson, J.5
-
100
-
-
0036953769
-
"Automatically Characterizing Large Scale Program Behavior"
-
T. Sherwood, E. Perelman, G. Hamerly, and B. Calder, "Automatically Characterizing Large Scale Program Behavior," Proc. Int'l Conf. Architectural Support for Programming Languages and Operating Systems, 2002.
-
(2002)
Proc. Int'l Conf. Architectural Support for Programming Languages and Operating Systems
-
-
Sherwood, T.1
Perelman, E.2
Hamerly, G.3
Calder, B.4
-
101
-
-
32044444511
-
-
http://research.compaq.com/wrl/projects/SimOS/SimOs.html, 2004.
-
(2004)
-
-
-
102
-
-
32044451201
-
-
http://www.research.ibm.com/arl/projects/SimOSppc.html, 2006.
-
(2006)
-
-
-
103
-
-
0002255264
-
"SPLASH: The Stanford ParalleL Application for SHared Memory"
-
J. Singh, W. Weber, and A. Gupta, "SPLASH: The Stanford ParalleL Application for SHared Memory," Computer Architecture News, vol. 20, no. 1, pp. 5-44, 1992.
-
(1992)
Computer Architecture News
, vol.20
, Issue.1
, pp. 5-44
-
-
Singh, J.1
Weber, W.2
Gupta, A.3
-
104
-
-
0033220924
-
"Branch Prediction, Instruction-Window Size, and Cache Size: Performance Trade-Offs and Simulation Techniques"
-
Nov
-
K. Skadron, P. Ahuja, M. Martonosi, and D. Clark, "Branch Prediction, Instruction-Window Size, and Cache Size: Performance Trade-Offs and Simulation Techniques," IEEE Trans. Computers, vol. 48, no. 11, pp. 1260-1281, Nov. 1999.
-
(1999)
IEEE Trans. Computers
, vol.48
, Issue.11
, pp. 1260-1281
-
-
Skadron, K.1
Ahuja, P.2
Martonosi, M.3
Clark, D.4
-
105
-
-
32044434553
-
-
http://www.spec.org/benchmarks.html, 2006.
-
(2006)
-
-
-
106
-
-
32044456842
-
-
http://www.spec.org/hpg, 2006.
-
(2006)
-
-
-
107
-
-
32044463476
-
-
http://www.specbench.org/jbb2000, 2006.
-
(2006)
-
-
-
108
-
-
32044448847
-
-
http://www.specbench.org/jvm98, 2006.
-
(2006)
-
-
-
109
-
-
32044474335
-
-
http://www.futuremark.com/products/sysmark2004, 2006.
-
(2006)
-
-
-
110
-
-
32044474546
-
-
http://www.tpc.org, 2006.
-
(2006)
-
-
-
111
-
-
84983179859
-
"Microarchitectural Exploration with Liberty"
-
M. Vachharajani, N. Vachharajani, D. Penry, J. Blome, and D. August, "Microarchitectural Exploration with Liberty," Proc. Int'l Symp. Microarchitecture, 2002.
-
(2002)
Proc. Int'l Symp. Microarchitecture
-
-
Vachharajani, M.1
Vachharajani, N.2
Penry, D.3
Blome, J.4
August, D.5
-
112
-
-
32044475279
-
"The Liberty Simulation Environment, Version 1.0"
-
Mar
-
M. Vachharajani, N. Vachharajani, D. Penry, J. Blome, and D. August, "The Liberty Simulation Environment, Version 1.0," Performance Evaluation Review: Special Issue on Tools for Architecture Research, vol. 31, no. 4, Mar. 2004.
-
(2004)
Performance Evaluation Review: Special Issue on Tools for Architecture Research
, vol.31
, Issue.4
-
-
Vachharajani, M.1
Vachharajani, N.2
Penry, D.3
Blome, J.4
August, D.5
-
119
-
-
0033700756
-
"Energy-Driven Integrated Hardware-Software Optimizations Using SimplePower"
-
N. Vijaykrishnan, M. Kandemir, M. Irwin, H. Kim, and W. Ye, "Energy-Driven Integrated Hardware-Software Optimizations Using SimplePower," Proc. Int'l Symp. Computer Architecture, 2000.
-
(2000)
Proc. Int'l Symp. Computer Architecture
-
-
Vijaykrishnan, N.1
Kandemir, M.2
Irwin, M.3
Kim, H.4
Ye, W.5
-
120
-
-
32044459828
-
"Introduction to the Simics Full-System Simulator without Equal"
-
Virtutech White Paper
-
"Introduction to the Simics Full-System Simulator without Equal," Virtutech White Paper, 2002.
-
(2002)
-
-
-
121
-
-
32044471180
-
-
http://www.volano.com/benchmarks.html, 2006.
-
(2006)
-
-
-
122
-
-
84976706468
-
"Efficient Trace-Driven Simulation Methods for Cache Performance Analysis"
-
Aug
-
W. Wang and J. Baer, "Efficient Trace-Driven Simulation Methods for Cache Performance Analysis," ACM Trans. Computer Systems, vol. 9, no. 3, pp. 222-241, Aug. 1991.
-
(1991)
ACM Trans. Computer Systems
, vol.9
, Issue.3
, pp. 222-241
-
-
Wang, W.1
Baer, J.2
-
123
-
-
0025568269
-
"An Overview of Common Benchmarks"
-
Dec
-
R. Weicker, "An Overview of Common Benchmarks," Computer, vol. 23, no. 12, pp. 65-75, Dec. 1990.
-
(1990)
Computer
, vol.23
, Issue.12
, pp. 65-75
-
-
Weicker, R.1
-
124
-
-
0033299119
-
"The Standardization of Embedded Benchmarking: Pitfalls and Opportunities"
-
A. Weiss, "The Standardization of Embedded Benchmarking: Pitfalls and Opportunities," Proc. Int'l Conf. Computer Design, 1999.
-
(1999)
Proc. Int'l Conf. Computer Design
-
-
Weiss, A.1
-
125
-
-
33744462550
-
"TurboSMARTS: Accurate Microarchitecture Simulation Sampling in Minutes"
-
Poster at the Int'l Conf. Measurement and Modeling of Computer Systems
-
T. Wenisch, R. Wunderlich, B. Falsafi, and J. Hoe, "TurboSMARTS: Accurate Microarchitecture Simulation Sampling in Minutes," Poster at the Int'l Conf. Measurement and Modeling of Computer Systems, 2005.
-
(2005)
-
-
Wenisch, T.1
Wunderlich, R.2
Falsafi, B.3
Hoe, J.4
-
128
-
-
0029179077
-
"The SPLASH-2 Programs: Characterization and Methodological Considerations"
-
S. Woo, M. Ohara, E. Torrie, J. Singh, and A. Gupta, "The SPLASH-2 Programs: Characterization and Methodological Considerations," Proc. Int'l Symp. Computer Architecture, 1995.
-
(1995)
Proc. Int'l Symp. Computer Architecture
-
-
Woo, S.1
Ohara, M.2
Torrie, E.3
Singh, J.4
Gupta, A.5
-
130
-
-
0038346244
-
"SMARTS: Accelerating Microarchitectural Simulation via Rigorous Statistical Sampling"
-
R. Wunderlich, T. Wenisch, B. Falsafi, and J. Hoe, "SMARTS: Accelerating Microarchitectural Simulation via Rigorous Statistical Sampling," Proc. Int'l Symp. Computer Architecture, 2003.
-
(2003)
Proc. Int'l Symp. Computer Architecture
-
-
Wunderlich, R.1
Wenisch, T.2
Falsafi, B.3
Hoe, J.4
-
131
-
-
33947721174
-
"An Evaluation of Stratified Sampling of Microarchitecture Simulations"
-
R. Wunderlich, T. Wenisch, B. Falsafi, and J. Hoe, "An Evaluation of Stratified Sampling of Microarchitecture Simulations," Proc. Workshop Duplicating, Deconstructing, and Debunking, 2004.
-
(2004)
Proc. Workshop Duplicating, Deconstructing, and Debunking
-
-
Wunderlich, R.1
Wenisch, T.2
Falsafi, B.3
Hoe, J.4
-
133
-
-
28444474809
-
"Characterizing and Comparing Prevailing Simulation Methodologies"
-
J. Yi, S. Kodakara, R. Sendag, D. Lilja, and D. Hawkins, "Characterizing and Comparing Prevailing Simulation Methodologies," Proc. Int'l Symp. High-Performance Computer Architecture, 2005.
-
(2005)
Proc. Int'l Symp. High-Performance Computer Architecture
-
-
Yi, J.1
Kodakara, S.2
Sendag, R.3
Lilja, D.4
Hawkins, D.5
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