Efficient simulation of trace samples on parallel machines

Parallel Computing

Volumn 30, Issue 3, 2004, Pages 317-335

  Eeckhout, Lieven ^a   De Bosschere, Koen ^a  

^a GHENT UNIVERSITY   (Belgium)

Author keywords

Cold start problem; Computer architecture; Parallel trace sampling; Performance analysis

Indexed keywords

BENCHMARKING; COMPUTER ARCHITECTURE; COMPUTER SIMULATION; MICROPROCESSOR CHIPS; PROBLEM SOLVING; SAMPLING;

COLD-START PROBLEMS; PARALLEL TRACE SAMPLING; PERFORMANCE ANALYSIS;

PARALLEL PROCESSING SYSTEMS;

EID: 1842852992     PISSN: 01678191     EISSN: None     Source Type: Journal    
DOI: 10.1016/j.parco.2004.02.003     Document Type: Article

References (29)

1. P. Bose, Performance evaluation and validation of microprocessors, in: Proceedings of the International Conference on Measurement and Modeling of Computer Systems (SIGMETRICS'99), May 1999, pp. 226-227.
2. Bose P., Conte T.M. Performance analysis and its impact on design. IEEE Computer. 31(5):1998;41-49.
3. Bose P., Conte T.M., Austin T.M. Challenges in processor modeling and validation. IEEE Micro. 19(3):1999;9-14.
4. T.M. Conte, Systematic Computer Architecture Prototyping. PhD Thesis, University of Illinois at Urbana-Champaign, (1992).
5. Conte T.M., Hirsch M.A., Hwu W.W. Combining trace sampling with single pass methods for efficient cache simulation. IEEE Transactions on Computers. 47:1998;714-720.
6. T.M. Conte, M.A. Hirsch, K.N. Menezes, Reducing state loss for effective trace sampling of superscalar processors, in: Proceedings of the 1996 International Conference on Computer Design (ICCD-96), October 1996, pp. 468-477.
7. P. Crowley, J.-L. Baer, Trace sampling for desktop applications on windows NT. in: Proceedings of the First Workshop on Workload Characterization (WWC-1998) held in conjunction with the 31st ACM/IEEE Annual International Symposium on Microarchitecture (MICRO-31), November 1998.
8. P.K. Dubey, R. Nair, Profile-driven sampled trace generation. Technical Report RC 20041, IBM Research Division, T.J. Watson Research Center, April 1995.
9. L. Eeckhout, S. Eyerman, B. Callens, K. De Bosschere, Accurately warmed-up trace samples for the evaluation of cache memories, in: Proceedings of the 2003 High Performance Computing Symposium (HPC-2003), April 2003, pp. 267-274.
10. J.W. Haskins Jr., K. Skadron, Minimal subset evaluation: Rapid warm-up for simulated hardware state. in: Proceedings of the 2001 International Conference on Computer Design (ICCD-2001), September 2001, pp. 32-39.
11. J.W. Haskins Jr., K. Skadron, Memory reference reuse latency: accelerated sampled microarchitecture simulation. Technical Report CS-2002-19, Department of Computer Science, University of Virginia, July 2002.
12. V.S. Iyengar, L.H. Trevillyan, Evaluation and generation of reduced traces for benchmarks. Technical Report RC 20610, IBM Research Division, T.J. Watson Research Center, October 1996.
13. V.S. Iyengar, L.H. Trevillyan, P. Bose, Representative traces for processor models with infinite cache. in: Proceedings of the Second International Symposium on High-Performance Computer Architecture (HPCA-2), February 1996, pp. 62-73.
14. J.J.W. Haskins, K. Skadron, Memory Reference Reuse Latency: Accelerated warmup for sampled microarchitecture simulation, in: Proceedings of the 2003 IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS-2003), March 2003, pp. 195-203.
15. Kessler R.E., Hill M.D., Wood D.A. A comparison of trace-sampling techniques for multi-megabyte caches. IEEE Transactions on Computers. 43(6):1994;664-675.
16. Khalid H. Validating trace-driven microarchitectural simulations. IEEE Micro. 20(6):2000;76-82.
17. T. Lafage, A. Seznec, Choosing representative slices of program execution for microarchitecture simulations: A preliminary application to the data stream. in: IEEE 3rd Annual Workshop on Workload Characterization (WWC-2000) held in conjunction with the International Conference on Computer Design (ICCD-2000), September 2000.
18. Laha S., Patel J.H., Iyer R.K. Accurate low-cost methods for performance evaluation of cache memory systems. IEEE Transactions on Computers. 37(11):1988;1325-1336.
19. G. Lauterbach, Accelerating architectural simulation by parallel execution of trace samples, Technical Report SMLI TR-93-22, Sun Microsystems Laboratories Inc., December 1993.
20. M. Martonosi, A. Gupta, T. Anderson. Effectiveness of trace sampling for performance debugging tools, in: Proceedings of the 1993 ACM SIGMETRICS Conference on Measurement and Modeling of Computer Systems, May 1993, pp. 248-259.
21. A.-T. Nguyen, P. Bose, K. Ekanadham, A. Nanda, M. Michael, Accuracy and speed-up of parallel trace-driven architectural simulation, in: Proceedings of the 11th International Parallel Processing Symposium (IPPS'97), April 1997, pp. 39-44.
22. Poursepanj A. The PowerPC performance modeling methodology. Communications of the ACM. 37(6):1994;47-55.
23. Reilly M. Designing an Alpha microprocessor. IEEE Computer. 32(7):1999;27-34.
24. T. Sherwood, E. Perelman, B. Calder, Basic block distribution analysis to find periodic behavior and simulation points in applications, in: Proceedings of the 2001 International Conference on Parallel Architectures and Compilation Techniques (PACT-2001), September 2001, pp. 3-14.
25. T. Sherwood, E. Perelman, G. Hamerly, B. Calder, Automatically characterizing large scale program behavior, in: Proceedings of the Tenth International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS-X), October 2002, pp. 45-57.
26. Skadron K., Ahuja P.S., Martonosi M., Clark D.W. Branch prediction, instruction-window size, and cache size: Performance tradeoffs and simulation techniques. IEEE Transactions on Computers. 48(11):1999;1260-1281.
27. Stone H.S. High-Performance Computer Architecture. 1987;Addison-Wesley Publishing Company.
28. D.A. Wood, M.D. Hill, R.E. Kessler, A model for estimating trace-sample miss ratios, in: Proceedings of the 1991 SIGMETRICS Conference on Measurement and Modeling of Computer Systems, May 1991, pp. 79-89.
29. R.E. Wunderlich, T.F. Wenish, B. Falsafi, J.C. Hoe. SMARTS: accelerating microarchitecture simulation via rigorous statistical sampling, in: Proceedings of the 30th Annual International Symposium on Computer Architecture (ISCA-30), June 2003.