Memory reference reuse latency: Accelerated warmup for sampled microarchitecture simulation

2003 IEEE International Symposium on Performance Analysis of Systems and Software, ISPASS 2003

Volumn , Issue , 2003, Pages 195-203

  Haskins, J W ^a   Skadron, K ^b  

^a Center for Computing Sciences   (United States)

^b University of Virginia   (United States)

Author keywords

Acceleration; Computational modeling; Computer architecture; Computer simulation; Delay; Hardware; Microarchitecture; Microprocessors; Predictive models; Throughput

Indexed keywords

ACCELERATION; COMPUTER ARCHITECTURE; COMPUTER HARDWARE; COMPUTER SIMULATION; MICROPROCESSOR CHIPS; PROGRAM PROCESSORS; THROUGHPUT;

COMPUTATIONAL MODEL; DELAY; INSTRUCTION STREAMS; MEMORY REFERENCE REUSE LATENCIES; MICRO ARCHITECTURES; MICROPROCESSOR SIMULATION; PREDICTIVE MODELS; RUNNING SIMULATIONS;

CACHE MEMORY;

EID: 84943402809     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISPASS.2003.1190246     Document Type: Conference Paper

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