Challenges in processor modeling and validation

IEEE Micro

Volumn 19, Issue 3, 1999, Pages 9-14

  Bose, Pradip ^a   Conte, Thomas M ^a   Austin, Todd M ^a  

^a IBM T J WATSON RESEARCH CENTER   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CYCLES PER INSTRUCTION; FINITE STATE MACHINE; REGISTER TRANSFER LEVEL;

COMPUTATIONAL COMPLEXITY; COMPUTER DEBUGGING; COMPUTER SIMULATION; COMPUTER SOFTWARE; FINITE AUTOMATA; FORMAL LOGIC; SYSTEMS ANALYSIS;

MICROPROCESSOR CHIPS;

EID: 0032658099     PISSN: 02721732     EISSN: None     Source Type: Journal    
DOI: 10.1109/MM.1999.768495     Document Type: Article

References (10)