Design and validation of a performance and power simulator for PowerPC systems

IBM Journal of Research and Development

Volumn 47, Issue 5-6, 2003, Pages 641-651

  Shafi, Hazim ^a   Bohrer, Patrick J ^a   Phelan, James ^b   Rusu, Cosmin A ^c   Peterson, James L ^a  

^a IBM AUSTIN RESEARCH LABORATORY   (United States)

^b IBM   (United States)

^c University of Pittsburgh   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CACHE MEMORY; COMPUTER SIMULATION; ELECTRIC POWER UTILIZATION; ENERGY EFFICIENCY; MICROPROCESSOR CHIPS;

POWER CONSUMPTION; TRANSLATION LOOKASIDE BUFFERS (TLB);

PROGRAM PROCESSORS;

EID: 0348158498     PISSN: 00188646     EISSN: None     Source Type: Journal    
DOI: 10.1147/rd.475.0641     Document Type: Article

References (15)

1. L. W. Nagel and D. O. Pederson, "Simulation Program with Integrated Circuit Emphasis," Memorandum ERL-M382, University of California at Berkeley, California, April 1973.
2. Sequence Design Inc., "PowerTheater Datasheet," Santa Clara, CA; see http://www.sequencedesign.com/2_solutions/powertheater3.pdf, 2002.
3. Synopsys Inc., "PowerMill Datasheet," Mountain View, CA.; see http://www.synopsys.com/products/etg/powermill_ds.html, 2002.
4. D. Brooks, V. Tiwari, and M. Martonosi, "Wattch: A Framework for Architectural-Level Power Analysis and Optimizations," Proceedings of the 27th Annual International Symposium on Computer Architecture, 2000, pp. 83-94.
5. F. Bellosa, "The Case for Event-Driven Energy Accounting," Technical Report TR-14-01, Friedrich Alexander Universitat Erlanger-Nurnberg, June 2001.
6. IBM Corporation, PowerPC 405GP Embedded Processor User's Manual. 9th Preliminary ed., 2001; see http://www.ibm.com/chips/techlib/techlib.nsf/products/ PowerPC_405GP_Embedded_Processor/.
7. A. R. Weiss, "The Standardization of Embedded Benchmarking: Pitfalls and Opportunities," Proceedings of the IEEE International Conference on Computer Design, October 1999, pp. 492-498.
8. M. Rosenblum, E. Bugnion, S. Devine, and S. Herrod, "Using the SimOS Machine Simulator to Study Complex Computer Systems," ACM Trans. Modeling & Computer Simulation 7, 78-103 (1997).
9. G. R. Ganger, "System-Oriented Evaluation of I/O Subsystem Performance," Ph.D. Dissertation, University of Michigan, Ann Arbor, June 1995.
10. Embedded Microprocessor Benchmark Consortium, "EEMBC Technical and Operating Specification; see www.eembc.org/, 2002.
11. S. Lee, A. Ermedahl, and S. L. Min, "An Accurate Instruction-Level Energy Consumption Model for Embedded RISC Processors," Proceedings of the ACM SIGPLAN Workshop on Languages, Compilers, and Tools for Embedded Systems (LCTES), 2001, pp. 1-10.
12. D. Burger and T. Austin, "The SimpleScalar Tool Set, Version 2.0," Computer Architecture News, pp. 13-25 (1997).
13. R. Joseph and M. Martonosi, "Run-Time Power Estimation in High-Performance Microprocessors," Proceedings of the International Symposium on Low Power Electronics and Design (ISLPED), August 2001.
14. V. Tiwari, S. Malik, and A. Wolfe, "Instruction Level Power Analysis and Optimization of Software," J. VLSI Signal Process. Syst. 13, 223-233 (1996).
15. IBM Corporation, PowerPC 405LP Embedded Processor, 2003; see http://www.ibm.com/chips/techlib/techlib.nsf/products/ PowerPC_405LP_Embedded_Processor/.