-
2
-
-
0017983865
-
Binary decision diagrams
-
S.B. Akers. Binary decision diagrams. IEEE Trans. on Comp., 27:509-516, 1978.
-
(1978)
IEEE Trans. on Comp.
, vol.27
, pp. 509-516
-
-
Akers, S.B.1
-
4
-
-
0029485365
-
Fast functional simulation using branching programs
-
P. Ashar and S. Malik. Fast functional simulation using branching programs. In Int'l Conf. on CAD, pages 408-412, 1995.
-
(1995)
Int'l Conf. on CAD
, pp. 408-412
-
-
Ashar, P.1
Malik, S.2
-
5
-
-
84944319371
-
Symbolic model checking without BDDs
-
Springer Verlag
-
A. Biere, A. Cimatti, E. Clarke, and Y. Zhu. Symbolic model checking without BDDs. In Tools and Algorithms for the Construction and Analysis of Systems, volume 1579 of Lecture Notes in Computer Science. Springer Verlag, 1999.
-
(1999)
Tools and Algorithms for the Construction and Analysis of Systems, Volume 1579 of Lecture Notes in Computer Science
-
-
Biere, A.1
Cimatti, A.2
Clarke, E.3
Zhu, Y.4
-
7
-
-
0032308363
-
Testing with decision diagrams
-
PII S0167926098000182
-
B. Becker. Testing with decision diagrams. INTEGRATION, the VLSI Jour., 26:5-20, 1998. (Pubitemid 128409231)
-
(1998)
Integration, the VLSI Journal
, vol.26
, Issue.1-2
, pp. 5-20
-
-
Becker, B.1
-
10
-
-
13544249131
-
On the effect of local changes in the variable ordering of ordered decision diagrams
-
DOI 10.1016/0020-0190(96)00119-6, PII S0020019096001196
-
B. Bollig, M. Löbbing, and I. Wegener. On the effect of local changes in the variable ordering of ordered decision diagrams. Information Processing Letters, 59:233-239, 1996. (Pubitemid 126392865)
-
(1996)
Information Processing Letters
, vol.59
, Issue.5
, pp. 233-239
-
-
Bollig, B.1
Lobbing, M.2
Wegener, I.3
-
11
-
-
2442546302
-
Telescopic units: Increasing the average throughput of pipelined designs by adaptive latency control
-
L. Benini, E. Macii, and M. Poncino. Telescopic units: Increasing the average throughput of pipelined designs by adaptive latency control. In Design Automation Conf., pages 22-27, 1997.
-
(1997)
Design Automation Conf.
, pp. 22-27
-
-
Benini, L.1
Macii, E.2
Poncino, M.3
-
12
-
-
0031340523
-
Logic synthesis for large pass transistor circuits
-
P. Buch, A. Narayan, A. Newton, and A. Sangiovanni-Vincentelli. Logic synthesis for large pass transistor circuits. In Int'l Conf. on CAD, pages 663-670, 1997.
-
(1997)
Int'l Conf. on CAD
, pp. 663-670
-
-
Buch, P.1
Narayan, A.2
Newton, A.3
Sangiovanni-Vincentelli, A.4
-
14
-
-
0022769976
-
Graph-based algorithms for boolean function manipulation
-
R. E. Bryant. Graph-based algorithms for Boolean function manipulation. IEEE Trans. on Comp., 35(8):677-691, 1986.
-
(1986)
IEEE Trans. on Comp.
, vol.35
, Issue.8
, pp. 677-691
-
-
Bryant, R.E.1
-
15
-
-
0026107125
-
On the complexity of VLSI implementations and graph representations of boolean functions with application to integer multiplication
-
R. E. Bryant. On the complexity of VLSI implementations and graph representations of Boolean functions with application to integer multiplication. IEEE Trans. on Comp., 40:205-213, 1991.
-
(1991)
IEEE Trans. on Comp.
, vol.40
, pp. 205-213
-
-
Bryant, R.E.1
-
16
-
-
0032320169
-
Tight integration of combinational verification methods
-
J.R. Burch and V. Singhal. Tight integration of combinational verification methods. In Int'l Conf. on CAD, pages 570-576, 1998.
-
(1998)
Int'l Conf. on CAD
, pp. 570-576
-
-
Burch, J.R.1
Singhal, V.2
-
17
-
-
0030246260
-
Improving the variable ordering of OBDDs is NP-complete
-
B. Bollig and I. Wegener. Improving the variable ordering of OBDDs in NP-complete. IEEE Trans. on Comp., 45(9):993-1002, 1996. (Pubitemid 126768781)
-
(1996)
IEEE Transactions on Computers
, vol.45
, Issue.9
, pp. 993-1002
-
-
Bollig, B.1
Wegener, I.2
-
19
-
-
0032301257
-
Area-oriented synthesis for pass-transistor logic
-
R. Chaudhry, T.-H. Liu, A. Aziz, and J.L. Burns. Area-oriented synthesis for pass-transistor logic. In Int'l Conf. on Comp. Design, pages 160-167, 1998.
-
(1998)
Int'l Conf. on Comp. Design
, pp. 160-167
-
-
Chaudhry, R.1
Liu, T.-H.2
Aziz, A.3
Burns, J.L.4
-
20
-
-
84893802558
-
SAT-based bounded model checking by means of BDD-based approximate traversals
-
G. Cabodi, S. Nocco, and S. Quer. SAT-based bounded model checking by means of BDD-based approximate traversals. In Design, Automation and Test in Europe, pages 898-903, 2003.
-
(2003)
Design, Automation and Test in Europe
, pp. 898-903
-
-
Cabodi, G.1
Nocco, S.2
Quer, S.3
-
21
-
-
0346812384
-
-
Collaborative Benchmarking Laboratory North Carolina State University, Department of Computer Science
-
Collaborative Benchmarking Laboratory. 1993 LGSynth Benchmarks. North Carolina State University, Department of Computer Science, 1993.
-
(1993)
1993 LGSynth Benchmarks
-
-
-
23
-
-
0034156689
-
Fast exact minimization of BDDs
-
R. Drechsler, N. Drechsler, and W. Günther. Fast exact minimization of BDDs. IEEE Trans. on CAD, 19(3):384-389, 2000.
-
(2000)
IEEE Trans. on CAD
, vol.19
, Issue.3
, pp. 384-389
-
-
Drechsler, R.1
Drechsler, N.2
Günther, W.3
-
26
-
-
84958959413
-
-
chapter Learning heuristics for OBDD minimization by evolutionary algorithms Springer Verlag
-
R. Drechsler, N. Göckel, and B. Becker. Parallel Problem Solving from Nature, volume 577 of LNCS, chapter Learning heuristics for OBDD minimization by evolutionary algorithms, pages 730-739. Springer Verlag, 1996.
-
(1996)
Parallel Problem Solving from Nature, Volume 577 of LNCS
, pp. 730-739
-
-
Drechsler, R.1
Göckel, N.2
Becker, B.3
-
27
-
-
0035063566
-
Using lower bounds during dynamic BDD minimization
-
DOI 10.1109/43.905674, PII S0278007001003517
-
R. Drechsler, W. Günther, and F. Somenzi. Using lower bounds during dynamic BDD minimization. IEEE Trans. on CAD, 20(1):51-57, 2001. (Pubitemid 32296863)
-
(2001)
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
, vol.20
, Issue.1
, pp. 51-57
-
-
Drechsler, R.1
Gunther, W.2
Somenzi, F.3
-
30
-
-
84881072062
-
A computing procedure for quantification theory
-
M. Davis and H. Putnam. A computing procedure for quantification theory. Journal of the ACM, 7:506-521, 1960.
-
(1960)
Journal of the ACM
, vol.7
, pp. 506-521
-
-
Davis, M.1
Putnam, H.2
-
32
-
-
1642312095
-
Synthesis of fully testable circuits from BDDs
-
R. Drechsler, J. Shi, and G. Fey. Synthesis of fully testable circuits from BDDs. IEEE Trans. on CAD, 23(3):440-443, 2004.
-
(2004)
IEEE Trans. on CAD
, vol.23
, Issue.3
, pp. 440-443
-
-
Drechsler, R.1
Shi, J.2
Fey, G.3
-
33
-
-
0037743816
-
Reducing the number of variable movements in exact BDD minimization
-
R. Ebendt. Reducing the number of variable movements in exact BDD minimization. In Int'l Symp. on Circuits and Systems, volume 5, pages 605-608, 2003.
-
(2003)
Int'l Symp. on Circuits and Systems
, vol.5
, pp. 605-608
-
-
Ebendt, R.1
-
35
-
-
2442561212
-
Combination of lower bounds in exact BDD minimization
-
R. Ebendt, W. Günther, and R. Drechsler. Combination of lower bounds in exact BDD minimization. In Design, Automation and Test in Europe, pages 758-763, 2003.
-
(2003)
Design, Automation and Test in Europe
, pp. 758-763
-
-
Ebendt, R.1
Günther, W.2
Drechsler, R.3
-
36
-
-
9144250993
-
An improved branch and bound algorithm for exact BDD minimization
-
R. Ebendt, W. Günther, and R. Drechsler. An improved branch and bound algorithm for exact BDD minimization. IEEE Trans. on CAD, 22(12):1657-1663, 2003.
-
(2003)
IEEE Trans. on CAD
, vol.22
, Issue.12
, pp. 1657-1663
-
-
Ebendt, R.1
Günther, W.2
Drechsler, R.3
-
39
-
-
27144456162
-
Combining ordered-best first search with branch and bound for exact BDD minimization
-
R. Ebendt, W. Günther, and R. Drechsler. Combining ordered-best first search with branch and bound for exact BDD minimization. IEEE Trans. on CAD, 2005.
-
(2005)
IEEE Trans. on CAD
-
-
Ebendt, R.1
Günther, W.2
Drechsler, R.3
-
40
-
-
0027208475
-
Calculation of rademacher-walsh spectral coefficients for systems of completely and incompletely specified boolean functions
-
B.J. Falkowski. Calculation of Rademacher-Walsh spectral coefficients for systems of completely and incompletely specified boolean functions. In IEEE Proceedings on Circuits, pages 1698-1701, 1993.
-
(1993)
IEEE Proceedings on Circuits
, pp. 1698-1701
-
-
Falkowski, B.J.1
-
44
-
-
0027047925
-
On variable ordering of binary decision diagrams for the application of multi-level logic synthesis
-
M. Fujita, Y. Matsunaga, and T. Kakuda. On variable ordering of binary decision diagrams for the application of multilevel synthesis. In European Conf. on Design Automation, pages 50-54, 1991. (Pubitemid 23584321)
-
(1992)
Proc Eur Conf Des Autom
, pp. 50-54
-
-
Fujita Masahiro1
Matsunaga Yusuke2
Kakuda Taeko3
-
45
-
-
0032311880
-
Symbolic algorithms for layout-oriented synthesis of pass transistor logic circuits
-
F. Ferrandi, A. Macii, E. Macii, M. Poncino, R. Scarsi, and F. Somenzi. Symbolic algorithms for layout-oriented synthesis of pass transistor logic circuits. In Int'l Conf. on CAD, pages 235-241, 1998.
-
(1998)
Int'l Conf. on CAD
, pp. 235-241
-
-
Ferrandi, F.1
Macii, A.2
Macii, E.3
Poncino, M.4
Scarsi, R.5
Somenzi, F.6
-
46
-
-
0027800929
-
Interleaving based variable ordering methods for ordered binary decision diagrams
-
H. Fujii, G. Ootomo, and C. Hori. Interleaving based variable ordering methods for ordered binary decision diagrams. In Int'l Conf. on CAD, pages 38-41, 1993.
-
(1993)
Int'l Conf. on CAD
, pp. 38-41
-
-
Fujii, H.1
Ootomo, G.2
Hori, C.3
-
47
-
-
0025432031
-
Finding the optimal variable ordering for binary decision diagrams
-
S.J. Friedman and K.J. Supowit. Finding the optimal variable ordering for binary decision diagrams. IEEE Trans. on Comp., 39(5):710-713, 1990.
-
(1990)
IEEE Trans. on Comp.
, vol.39
, Issue.5
, pp. 710-713
-
-
Friedman, S.J.1
Supowit, K.J.2
-
48
-
-
0027718374
-
An effective computer algorithm for the calculation of disjoint cube representation of boolean functions
-
B.J. Falkowski, I. Schäfer, and C.-H. Chang. An effective computer algorithm for the calculation of disjoint cube representation of boolean functions. In Midwest Symposium on Circuits and Systems, pages 1308-1311, 1993.
-
(1993)
Midwest Symposium on Circuits and Systems
, pp. 1308-1311
-
-
Falkowski, B.J.1
Schäfer, I.2
Chang, C.-H.3
-
51
-
-
35248874847
-
Abstraction and BDDs complement SAT-based BMC in DiVer
-
Springer-Verlag
-
A. Gupta, M. Ganai, C. Wang, Z. Yang, and P. Ashar. Abstraction and BDDs complement SAT-based BMC in DiVer. In International Conference on Computer Aided Verification, volume 2725 of Lecture Notes in Computer Science, pages 206-209. Springer-Verlag, 2003.
-
(2003)
International Conference on Computer Aided Verification, Volume 2725 of Lecture Notes in Computer Science
, pp. 206-209
-
-
Gupta, A.1
Ganai, M.2
Wang, C.3
Yang, Z.4
Ashar, P.5
-
53
-
-
0019543877
-
Implicit enumeration algorithm to generate tests for combinational logic circuits
-
P. Goel. An implicit enumeration algorithm to generate test for combinational logic. IEEE Trans. on Comp., 30:215-222, 1981. (Pubitemid 11487994)
-
(1981)
IEEE Transactions on Computers
, vol.C-30
, Issue.3
, pp. 215-222
-
-
Goel, P.1
-
54
-
-
0035215350
-
Partition-based decision heuristics for image computation using SAT and BDDs
-
A. Gupta, Z. Yang, P. Ashar, L. Zhang, and S. Malik. Partition-based decision heuristics for image computation using SAT and BDDs. In Int'l Conf. on CAD, pages 286-292, 2001. (Pubitemid 33148972)
-
(2001)
IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers
, pp. 286-292
-
-
Gupta, A.1
Yang, Z.2
Ashar, P.3
Zhang, L.4
Malik, S.5
-
55
-
-
84899829959
-
A formal basis for the heuristic determination of minimum cost paths
-
P.E. Hart, N.J. Nilsson, and B. Raphael. A formal basis for the heuristic determination of minimum cost paths. IEEE Trans. Syst. Sci. Cybern., 2:100-107, 1968.
-
(1968)
IEEE Trans. Syst. Sci. Cybern.
, vol.2
, pp. 100-107
-
-
Hart, P.E.1
Nilsson, N.J.2
Raphael, B.3
-
57
-
-
0027091090
-
Minimization of binary decision diagrams based on exchange of variables
-
N. Ishiura, H. Sawada, and S. Yajima. Minimization of binary decision diagrams based on exchange of variables. In Int'l Conf. on CAD, pages 472-475, 1991.
-
(1991)
Int'l Conf. on CAD
, pp. 472-475
-
-
Ishiura, N.1
Sawada, H.2
Yajima, S.3
-
58
-
-
0030718151
-
Postlayout logic restructuring for performance optimization
-
Y.-M. Jiang, A. Krstic, K.-T. Cheng, and M. Marek-Sadowska. Postlayout logic restructuring for performance optimization. In Design Automation Conf., pages 662-665, 1997.
-
(1997)
Design Automation Conf.
, pp. 662-665
-
-
Jiang, Y.-M.1
Krstic, A.2
Cheng, K.-T.3
Marek-Sadowska, M.4
-
60
-
-
0042090416
-
Generalized cofactoring for logic function evaluation
-
Y. Jiang, S. Matic, and R.K. Brayton. Generalized cofactoring for logic function evaluation. In Design Automation Conf., pages 155-158, 2003.
-
(2003)
Design Automation Conf.
, pp. 155-158
-
-
Jiang, Y.1
Matic, S.2
Brayton, R.K.3
-
65
-
-
0026623575
-
Test pattern generation using boolean satisfiability
-
T. Larrabee. Test pattern generation using Boolean satisfiability. IEEE Trans. on CAD, 11:4-15, 1992.
-
(1992)
IEEE Trans. on CAD
, vol.11
, pp. 4-15
-
-
Larrabee, T.1
-
66
-
-
84903828974
-
Representation of switching circuits by binary decision diagrams
-
C.Y. Lee. Representation of switching circuits by binary decision diagrams. Bell System Technical Jour., 38:985-999, 1959.
-
(1959)
Bell System Technical Jour.
, vol.38
, pp. 985-999
-
-
Lee, C.Y.1
-
68
-
-
3142706079
-
Binary decision diagram with minimum expected path length
-
Y. Y. Liu, K. H. Wang, T. T. Hwang, and C. L. Liu. Binary decision diagram with minimum expected path length. In Design, Automation and Test in Europe, pages 708-712, 2001.
-
(2001)
Design, Automation and Test in Europe
, pp. 708-712
-
-
Liu, Y.Y.1
Wang, K.H.2
Hwang, T.T.3
Liu, C.L.4
-
69
-
-
0017458236
-
On the complexity of admissable search algorithms
-
A. Martelli. On the complexity of admissable search algorithms. Artificial Intelligence, 23:1-13, 1977.
-
(1977)
Artificial Intelligence
, vol.23
, pp. 1-13
-
-
Martelli, A.1
-
70
-
-
0024131721
-
Proving circuit correctness using formal comparison between expected and extracted behavior
-
J.-C. Madre and J.-P. Billon. Proving circuit correctness using formal comparison between expected and extracted behavior. In Design Automation Conf., pages 205-210, 1988.
-
(1988)
Design Automation Conf.
, pp. 205-210
-
-
Madre, J.-C.1
Billon, J.-P.2
-
71
-
-
0038450554
-
On-the-fly layout generation for PTL macrocells
-
L. Macchiarulo, L. Benini, and E. Macii. On-the-fly layout generation for PTL macrocells. In Design, Automation and Test in Europe, pages 546-551, 2001.
-
(2001)
Design, Automation and Test in Europe
, pp. 546-551
-
-
Macchiarulo, L.1
Benini, L.2
Macii, E.3
-
75
-
-
0029492723
-
Fast discrete function evaluation using decision diagrams
-
P.C. McGeer, K.L. McMillan, A. Saldanha, A.L. Sangiovanni-Vincentelli, and P. Scaglia. Fast discrete function evaluation using decision diagrams. In Int'l Conf. on CAD, pages 402-407, 1995.
-
(1995)
Int'l Conf. on CAD
, pp. 402-407
-
-
McGeer, P.C.1
McMillan, K.L.2
Saldanha, A.3
Sangiovanni-Vincentelli, A.L.4
Scaglia, P.5
-
76
-
-
0034852165
-
Chaff: Engineering an efficient SAT solver
-
M.W. Moskewicz, C.F. Madigan, Y. Zhao, L. Zhang, and S. Malik. Chaff: Engineering an efficient SAT solver. In Design Automation Conf., pages 530-535, 2001. (Pubitemid 32841010)
-
(2001)
Proceedings-Design Automation Conference
, pp. 530-535
-
-
Moskewicz, M.W.1
Madigan, C.F.2
Zhao, Y.3
Zhang, L.4
Malik, S.5
-
77
-
-
0004899145
-
A heuristic search algorithm with modifiable estimate
-
L. Mérõ. A heuristic search algorithm with modifiable estimate. Artificial Intelligence, 23:13-27, 1984.
-
(1984)
Artificial Intelligence
, vol.23
, pp. 13-27
-
-
Mérõ, L.1
-
81
-
-
29244455141
-
Combinational equivalence checking using boolean satisfiability and recursive learning
-
J.P. Marques-Silva and T. Glass. Combinational equivalence checking using boolean satisfiability and recursive learning. In Design, Automation and Testin Europe, pages 145-149, 1999.
-
(1999)
Design, Automation and Testin Europe
, pp. 145-149
-
-
Marques-Silva, J.P.1
Glass, T.2
-
82
-
-
0032688693
-
Wave steering in YADDs: A novel, non-iterative synthesis and layout technique
-
A. Mukherjee, R. Sudhakar, M. Marek-Sadowska, and S. Long. Wave steering in YADDs: a novel, non-iterative synthesis and layout technique. In Design Automation Conf., pages 466-471, 1999.
-
(1999)
Design Automation Conf.
, pp. 466-471
-
-
Mukherjee, A.1
Sudhakar, R.2
Marek-Sadowska, M.3
Long, S.4
-
83
-
-
0030402207
-
GRASP-A new search algorithm for satisfiability
-
J.P. Marques-Silva and K.A. Sakallah. GRASP-a new search algorithm for satisfiability. In Int'l Conf. on CAD, pages 220-227, 1996.
-
(1996)
Int'l Conf. on CAD
, pp. 220-227
-
-
Marques-Silva, J.P.1
Sakallah, K.A.2
-
88
-
-
0033714065
-
Equivalence checking combining a structural SAT-solver, BDDs, and simulation
-
V. Paruthi and A. Kuehlmann. Equivalence checking combining a structural SAT-solver, BDDs, and simulation. In Int'l Conf. on Comp. Design, pages 459-464, 2000.
-
(2000)
Int'l Conf. on Comp. Design
, pp. 459-464
-
-
Paruthi, V.1
Kuehlmann, A.2
-
89
-
-
0029487141
-
Who are the variables in your neighbourhood
-
S. Panda and F. Somenzi. Who are the variables in your neighbourhood. In Int'l Conf. on CAD, pages 74-77, 1995.
-
(1995)
Int'l Conf. on CAD
, pp. 74-77
-
-
Panda, S.1
Somenzi, F.2
-
92
-
-
0031641253
-
Approximation and decomposition of binary decision diagrams
-
K. Ravi, K.L. McMillan, T.R. Shiple, and F. Somenzi. Approximation and decomposition of binary decision diagrams. In Design Automation Conf., pages 445-450, 1998.
-
(1998)
Design Automation Conf.
, pp. 445-450
-
-
Ravi, K.1
McMillan, K.L.2
Shiple, T.R.3
Somenzi, F.4
-
93
-
-
0029516742
-
High-density reachability analysis
-
K. Ravi and F. Somenzi. High-density reachability analysis. In Int'l Conf. on CAD, pages 154-158, 1995.
-
(1995)
Int'l Conf. on CAD
, pp. 154-158
-
-
Ravi, K.1
Somenzi, F.2
-
94
-
-
18844387149
-
Combinational equivalence checking using binary decision diagrams and boolean satisfiability
-
S. Reda and A. Salem. Combinational equivalence checking using binary decision diagrams and Boolean satisfiability. In Design, Automation and Test in Europe, pages 122-126, 2001.
-
(2001)
Design, Automation and Test in Europe
, pp. 122-126
-
-
Reda, S.1
Salem, A.2
-
95
-
-
0027841555
-
Dynamic variable ordering for ordered binary decision diagrams
-
R. Rudell. Dynamic variable ordering for ordered binary decision diagrams. In Int'l Conf. on CAD, pages 42-47, 1993.
-
(1993)
Int'l Conf. on CAD
, pp. 42-47
-
-
Rudell, R.1
-
96
-
-
0027593749
-
EXMIN2. A simplification algorithm for exclusive-or-sum-of products expressions for multiple-valued-input two-valued-output functions
-
DOI 10.1109/43.277608
-
T. Sasao. EXMIN2: A simplification algorithm for Exclusive-OR-Sum-of products expressions for multiple-valued-input two-valued-output functions. IEEE Trans. on CAD, 12:621-632, 1993. (Pubitemid 23700440)
-
(1993)
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
, vol.12
, Issue.5
, pp. 621-632
-
-
Sasao Tsutomu1
-
97
-
-
0001536086
-
On the generation of multiplexer circuits for pass transistor logic
-
C. Scholl and B. Becker. On the generation of multiplexer circuits for pass transistor logic. In Design, Automation and Test in Europe, pages 372-378, 2000.
-
(2000)
Design, Automation and Test in Europe
, pp. 372-378
-
-
Scholl, C.1
Becker, B.2
-
98
-
-
0010180487
-
Combinational test generation using satisfiability
-
Univ. of California, Berkeley, October
-
P. R. Stephan, R. K. Brayton, and A. Sangiovanni-Vincentelli. Combinational test generation using satisfiability. Technical Report UCB/ERL M92/112, Dept. of EECS, Univ. of California, Berkeley, October 1992.
-
(1992)
Technical Report UCB/ERL M92/112, Dept. of EECS
-
-
Stephan, P.R.1
Brayton, R.K.2
Sangiovanni-Vincentelli, A.3
-
99
-
-
0031365981
-
Functional simulation using binary decision diagrams
-
C. Scholl, R. Drechsler, and B. Becker. Functional simulation using binary decision diagrams. In Int'l Conf. on CAD, pages 8-12, 1997.
-
(1997)
Int'l Conf. on CAD
, pp. 8-12
-
-
Scholl, C.1
Drechsler, R.2
Becker, B.3
-
100
-
-
84932847893
-
A symbolic analysis of relay and switching circuits
-
C.E. Shannon. A symbolic analysis of relay and switching circuits. Trans. AIEE, 57:713-723, 1938.
-
(1938)
Trans. AIEE
, vol.57
, pp. 713-723
-
-
Shannon, C.E.1
-
102
-
-
84896694135
-
Efficient manipulation of decision diagrams
-
F. Somenzi. Efficient manipulation of decision diagrams. Software Tools for Technology Transfer, 3(2):171-181, 2001.
-
(2001)
Software Tools for Technology Transfer
, vol.3
, Issue.2
, pp. 171-181
-
-
Somenzi, F.1
-
104
-
-
0012932833
-
Computation of disjoint cube representations using a maximal binate variable heuristic
-
L. Shivakumaraiah and M. Thornton. Computation of disjoint cube representations using a maximal binate variable heuristic. In Southeastern Symposium on System Theory, pages 417-421, 2002.
-
(2002)
Southeastern Symposium on System Theory
, pp. 417-421
-
-
Shivakumaraiah, L.1
Thornton, M.2
-
107
-
-
0030166924
-
Top-down pass-transistor logic design
-
PII S0018920096042059
-
K. Yano, Y. Sasaki, K. Rikino, and K. Seki. Top-down pass transistor logic design. IEEE Jour. of Solid-State Circ., 31(6):792-803, 1996. (Pubitemid 126543793)
-
(1996)
IEEE Journal of Solid-State Circuits
, vol.31
, Issue.6
, pp. 792-803
-
-
Yano, K.1
Sasaki, Y.2
Rikino, K.3
Seki, K.4
|