Combinational equivalence checking using Boolean satisfiability and binary decision diagrams

Proceedings -Design, Automation and Test in Europe, DATE

Volumn , Issue , 2001, Pages 122-126

  Reda, Sherief ^a   Salem, Ashraf ^b  

^a The British University in Egypt   (Egypt)

^b MENTOR GRAPHICS CORPORATION   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

BENCHMARK CIRCUIT; BOOLEAN SATISFIABILITY; COMBINATIONAL EQUIVALENCE CHECKING; INDUSTRIAL CIRCUITS; ITS APPLICATIONS;

BENCHMARKING; BINARY DECISION DIAGRAMS; EXHIBITIONS;

EQUIVALENT CIRCUITS;

EID: 18844387149     PISSN: 15301591     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/DATE.2001.915011     Document Type: Conference Paper

References (18)

1. C. Leonard Berman, Louise H. Trevillyan. "Functional Comparison of Logic Circuits for VLSI Circuits", In Proceedings of International Conference on Computer-aided Design, Nov. 1989.
2. D. Brand, "Verification of Large Synthesized Designs", In Proceedings of International Conference on Computer-aided Design, 1993.
3. rd IEEE/ACM Design Automation Conference, 1996.
4. nd ACM/IEEE Design Automation Conference, June 1995.
5. th ACM/IEEE Design Automation Conference, 1997.
6. T. Larrabee, "Test Pattern generation Using Boolean Satisfiability", IEEE Trans. on Computer Aided Design, Vol. 11, No. 1, January 1992.
7. P. Stephan, Robert K. Brayton and Alberto L. Sangiovanni-Vincentelli, "Combinational Test generation Using Boolean Satisfiability", IEEE Trans. Computer Aided-Design of Integrated Circuits and Systems, Vol. 15, No. 9, September 1996.
8. nd ACM/IEEE Design Automation Conference, June 1995.
9. R. E. Bryant, "Graph-Based Algorithms for Boolean Function Manipulation", IEEE Trans. on Computers, Vol. C-35, No. 8, August 1986.
10. S. Malik, A. Wang, R. Brayton, A. Sangiovanni-Vincentelli, "Logic verification using Binary Decision Diagrams in a Logic Synthesis Environment", Int. Conf. On Computer Aided Design, 1988.
11. R. Rudell, "Dynamic Variable Ordering for Ordered Binary Decision Diagrams", In Proc. of Int. Conf. On Computer Aided Design, 1993.
12. M. Abramovici, M. A. Breuer, A. D. Friedman, Digital Systems Testing and Testable Design, IEEE Press, 1990.
13. A. Gupta and P. Ashar, "Integrating Boolean Satisfiability Checker and BDDs for Combinational equivalence Checking", In Proc. Intl. Conf. On VLSI Design, Chennai, India 1998.
14. J. Burch, V. Singhal. "Tight Integration of Combinational Verification Methods", International Conference on Computer Aided Design, 1998.
15. E. Cenry and C. Mauras, "Tautology Checking using crosscontrollability and cross-observability relations", In Proc. of IEEE International Conference on Computer Aided Design, 1990.
16. M. Schulz, E. Trischler and T. Sarfert, "SOCRATES: A Highly Efficient Automatic Test pattern Generation System", IEEE Trans. on Computer Aided Design, Vol. 7, No. 1, January 1988.
17. F. Somenzi, CUDD: Colorado University Decision Diagram Package. ftp://vlsi.colorado.edu/pub.
18. E. M. Sentovich, K. J. Singh, C. Moon, H. Savoj, R. K. Brayton, and A. Sangiovanni-Vincentelli. "Sequential circuit design synthesis and optimization", In Proc. Int. Conf. on Computer Design, 1992.