On the relation between SAT and BDDs for equivalence checking

Proceedings - International Symposium on Quality Electronic Design, ISQED

Volumn 2002-January, Issue , 2002, Pages 394-399

  Reda, S ^a   Drechsler, R ^b   Orailoglu, A ^a  

^a UNIVERSITY OF CALIFORNIA   (United States)

^b UNIVERSITY OF BREMEN   (Germany)

Author keywords

Art; Automatic test pattern generation; Binary decision diagrams; Boolean functions; Circuits; Computer science; Data structures; Decision trees

Indexed keywords

AUTOMATIC TEST PATTERN GENERATION; BINARY TREES; BINS; BOOLEAN ALGEBRA; BOOLEAN FUNCTIONS; COMPUTER SCIENCE; DATA STRUCTURES; DECISION TREES; FORMAL LOGIC; NETWORKS (CIRCUITS);

ART; BINARY DECISION DIAGRAMS (BDDS); BOOLEAN FORMULAE; BOOLEAN SATISFIABILITY; BOOLEAN SATISFIABILITY PROBLEMS; EQUIVALENCE CHECKING; MANIPULATION TECHNIQUES; VERIFICATION TOOLS;

BINARY DECISION DIAGRAMS;

EID: 4944249212     PISSN: 19483287     EISSN: 19483295     Source Type: Conference Proceeding    
DOI: 10.1109/ISQED.2002.996778     Document Type: Conference Paper

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