Buffer minimization in pass transistor logic

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Volumn 20, Issue 5, 2001, Pages 693-697

  Zhou, Hai ^a   Aziz, Adnan ^b  

^a SYNOPSYS INC   (United States)

^b The University of Texas at Austin   (United States)

Author keywords

Buffers; Pass transistor logic performance

Indexed keywords

ALGORITHMS; BUFFER STORAGE; COMPUTATIONAL COMPLEXITY; LOGIC CIRCUITS;

BUFFER INSERTION;

TRANSISTORS;

EID: 0035335648     PISSN: 02780070     EISSN: None     Source Type: Journal    
DOI: 10.1109/43.920711     Document Type: Article

References (14)

1. VIS: A system for verification and synthesis
2. Logic synthesis for large pass transistor circuits
3. Inverter minimization in multi-level logic networks
4. Overview of low-power ULSI circuit techniques
5. Differential cascade voltage switch with pass-gate (DCVSPG) logic tree for high performance CMOS digital systems
6. Simultaneous PTL buffer insertion and sizing for minimizing elmore delay
7. A high speed, low power, swing restored pass transistor logic based multiply and accumulate circuit for multimedia applications
8. Regenerative pass transistor logic: A circuit technique for high speed digital design
9. Top-down pass transistor logic design
10. A 3.8-ns CMOS 16 × 16-b multiplier using complementary pass transistor logic