Evaluation of multiple-output logic functions using decision diagrams

Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC

Volumn 2003-January, Issue , 2003, Pages 312-315

  Iguchi, Y ^a   Sasao, T ^b   Matsuura, M ^b  

^a MEIJI UNIVERSITY   (Japan)

^b KYUSHU INSTITUTE OF TECHNOLOGY   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

BOOLEAN FUNCTIONS; COMMUNICATION CHANNELS (INFORMATION THEORY); COMPUTATION THEORY; COMPUTER AIDED DESIGN; COMPUTER CIRCUITS; DECISION THEORY; FADING CHANNELS; RECONFIGURABLE HARDWARE;

BENCHMARK FUNCTIONS; CHARACTERISTIC FUNCTIONS; COMPUTATION TIME; DECISION DIAGRAM; EXPERIMENTAL ANALYSIS; LOGIC FUNCTIONS; MULTI-TERMINAL BDD; MULTIPLE OUTPUTS;

FUNCTION EVALUATION;

EID: 0038584164     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ASPDAC.2003.1195034     Document Type: Conference Paper

References (9)

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