Post-layout logic restructuring for performance optimization

Proceedings - Design Automation Conference

Volumn , Issue , 1997, Pages 662-665

  Jiang, Yi Min ^a   Krstic, Angela ^a   Cheng, Kwang Ting ^a   Marek Sadowska, Malgorzata ^a  

^a UNIVERSITY OF CALIFORNIA   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ELECTRIC WIRING; INTEGRATED CIRCUIT TESTING; OPTIMIZATION; PERFORMANCE; STANDARDS;

BENCHMARK CIRCUIT; BERKELEY SYNTHESIS SYSTEM; LOGIC SYNTHESIS;

LOGIC DESIGN;

EID: 0030718151     PISSN: 0738100X     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/266021.266313     Document Type: Conference Paper

References (7)