BDD circuit optimization for path delay fault testability

Proceedings of the EUROMICRO Systems on Digital System Design, DSD 2004

Volumn , Issue , 2004, Pages 168-172

  Fey, Görschwin ^a   Shi, Junhao ^a   Drechsler, Rolf ^a  

^a UNIVERSITY OF BREMEN   (Germany)

Author keywords

[No Author keywords available]

Indexed keywords

BINARY DECISION DIAGRAM (BDD); PATH DELAY FAULT TESTABILITY; SYMBOLIC METHODS; TECHNOLOGY MAPPING;

COMPUTATIONAL COMPLEXITY; FUNCTIONS; GRAPHIC METHODS; HEURISTIC METHODS; MATHEMATICAL MODELS; MULTIPLEXING; OPTIMIZATION;

NETWORKS (CIRCUITS);

EID: 13944280272     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/DSD.2004.1333273     Document Type: Conference Paper

References (19)

1. P. Ashar, S. Devadas, and K. Keutzer. Path-delay-fault testability properties of multiplexor-based networks. INTEGRATION, the VLSI Jour., 15(1): 1-23, 1993.
2. B. Becker. Synthesis for testability: Binary decision diagrams. In Symp. on Theoretical Aspects of Comp. Science, volume 577 of LNCS, pages 501-512. Springer Verlag, 1992.
3. B. Becker. Testing with decision diagrams. INTEGRATION, the VLSI Jour., 26:5-20, 1998.
4. B. Bollig and I. Wegener. Improving the variable ordering of OBDDs is NP-complete. IEEE Trans. on Comp., 45(9):993-1002, 1996.
5. R.E. Bryant. Graph-based algorithms for Boolean function manipulation. lEEE Trans. on Comp., 35(8):677-691, 1986.
6. R.E. Bryant. Binary decision diagrams and beyond: Enabling techniques for formal verification. In Int'l Conf. on CAD, pages 236-243, 1995.
7. R. Drechsler, J. Shi, and G. Fey. Synthesis of fully testable circuits from BDDs. IEEE Trans. on CAD, 23(3):440-443, 2004.
8. E.V. Dubrova and D.M. Miller. On disjoint covers and ROBDD size. In Pacific Rim Conference on Communications, Computers and Signal Processing, pages 162-164, 1999.
9. R. Ebendt, W. Günther, and R. Drechsler. Minimization of the expected path length in BDDs based on local changes. In ASP Design Automation Conf., pages 866-871, 2004.
10. G. Fey and R. Drechsler. Minimizing the number of paths in BDDs. In Symposium on Integrated Circuits and System Design, pages 359-364, 2002.
11. G. Fey and R. Drechsler. Utilizing BDDs for disjoint SOP minimization. In Midwest Symposium on Circuits and Systems, volume 2, pages 306-309, 2002.
12. W. Günther and R. Drechsler. ACTion: Combining logic synthesis and technology mapping for MUX based FPGAs. Journal of Systems Architecture, 46(14):132l-1334, 2000.
13. A. Kristić and K.-T. Cheng. Resynthesis of combinational circuits for path count reduction and for path delay fault testability. Jour. of Electronic Testing: Theory and Applications, 11:43-54, 1997.
14. I. Pomeranz and S. Reddy. Delay fault models for VLSI circuits. INTEGRATION, the VLSI Jour., 26:21-40, 1998.
15. I. Pomeranz and S. M. Reddy. Design-for-testability for path delay faults in combinational circuits using test points. IEEE Trans. on CAD, 17:333-343, 1998.
16. R. Rudell. Dynamic variable ordering for ordered binary decision diagrams. In Int'l Conf. on CAD, pages 42-47, 1993.
17. C. Scholl, R. Drechsler, and B. Becker. Functional simulation using binary decision diagrams. In Int'l Conf. on CAD, pages 8-12, 1997.
18. E. Sentovich, K. Singh, L. Lavagno, Ch. Moori, R. Murgai, A. Saldanha, H. Savoj, P. Stephan, R. Brayton, and A. Sangiovanni-Vincentelli. SIS: A system for sequential circuit synthesis. Technical report, University of Berkeley, 1992.
19. G.L. Smith. Model for delay faults based upon paths. In lnt'l Test Conf., pages 342-349, 1985.