Binary decision diagram with minimum expected path length

Proceedings -Design, Automation and Test in Europe, DATE

Volumn , Issue , 2001, Pages 708-712

  Liu, Yi Yu ^a   Wang, Kuo Hua ^b   Hwang, Tingting ^a   Liu, C L ^a  

^a NATIONAL TSING HUA UNIVERSITY   (Taiwan)

^b FU JEN CATHOLIC UNIVERSITY   (Taiwan)

Author keywords

[No Author keywords available]

Indexed keywords

BINARY DECISION DIAGRAMS (BDD); GENERIC DATA STRUCTURES; PATH LENGTH; ROOT NODES; TERMINAL NODES;

ALGORITHMS; BINARY DECISION DIAGRAMS; EXHIBITIONS;

BOOLEAN FUNCTIONS;

EID: 3142706079     PISSN: 15301591     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/DATE.2001.915105     Document Type: Conference Paper

References (8)

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2. R. E. Bryant, "Graph-based algorithms for boolean function manipulation", IEEE Trans. on Comput., Vol. C-35, No. 8, August 1986.
3. K. S. Brace, R. L. Rudell, and R. E. Bryant, "Efficient Implementation of a BDD Package", DAC, 1990.
4. R. Rudell, "Dynamic variables ordering for ordered binary decision diagrams", ICCAD, 1993.
5. M. Fujita, Y. Matsunaga, and T. Kakuda, "On Variable Ordering of Binary Decision Diagrams for the Application of Multi-level Logic Synthesis", EDAC, pp 50-54, Mar. 1991.
6. N. Ishiura, H. Sawada, and S. Yajima, "Minimization of Binary Decision Diagrams Based on Exchanges of Variables" ICCAD, pp. 472-475, Nov. 1991.
7. K. H. Wang, T. T. Hwang, and C. Chen, "Restructuring Binary Decision Diagrams Based on Functional Equivalence", EDAC, pp 261-265, Feb. 1993.
8. E. M. Sentovich, K. J. Singh, L. Lavagno, C. Moon, R. Murgai, A. Saldanha, H. Savoj, P. R. Stephan, R. K. Brayton, A. Sangiovanni-Vincentelli, "SIS: A System for Sequential Circuit Synthesis", Electronics Research Laboratory Memorandum No. UCB/ERL M 92/41, 4May 1992.