Using lower bounds during dynamic BDD minimization

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Volumn 20, Issue 1, 2001, Pages 51-57

  Drechsler, Rolf ^a,b   Günther, Wolfgang ^c   Somenzi, Fabio ^d  

^a IEEE   (Germany)

^b SIEMENS AG   (Germany)

^c UNIVERSITY OF FREIBURG   (Germany)

^d UCB 450   (United States)

Author keywords

BDDs; Lower bound; Minimization; Representation; Sifting; Variable ordering; Verification; VLSI CAD

Indexed keywords

BINARY DECISION DIAGRAMS (BDD);

ALGORITHMS; BOOLEAN FUNCTIONS; DATA STRUCTURES; DYNAMIC PROGRAMMING; OPTIMIZATION; VLSI CIRCUITS;

COMPUTER AIDED LOGIC DESIGN;

EID: 0035063566     PISSN: 02780070     EISSN: None     Source Type: Journal    
DOI: 10.1109/43.905674     Document Type: Article

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