Combination of lower bounds in exact BDD minimization

Proceedings -Design, Automation and Test in Europe, DATE

Volumn , Issue , 2003, Pages 758-763

  Ebendt, Rudiger ^a   Gunther, Wolfgang ^b   Drechsler, Rolf ^c  

^a France   (Germany)

^b INFINEON TECHNOLOGIES AG   (Germany)

^c UNIVERSITY OF BREMEN   (Germany)

Author keywords

[No Author keywords available]

Indexed keywords

FORMAL VERIFICATIONS; LOGIC SYNTHESIS; LOWER BOUNDS; NP COMPLETE; OPTIMAL VARIABLES; ORDERED BINARY DECISION DIAGRAMS; VARIABLE ORDER; VLSI DESIGN;

BOOLEAN FUNCTIONS; EXHIBITIONS;

BRANCH AND BOUND METHOD;

EID: 2442561212     PISSN: 15301591     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/DATE.2003.1253698     Document Type: Conference Paper

References (18)

1. [l) B. Bollig and I. Wegener. Improving the variable ordering of OBDDs is NP-complete. IEEE Trans. on Camp., 45(9):993-1002.1996
2. R. Bryant. Graph-based algorithms for Boolean function manipulation. IEEE Trans. on Camp 35(8):677-691,1986
3. R. Bryant. On the compl exity of VLSI implementations and graph repr esentations of Boolean functions with application to integer mUltiplication. IEEE Trans. on Camp . . 40:205-213,1991
4. P. Buch.A. Narayan , A. Newton, and A. Sangiovanni Vincentelli. Logic synthesis for large pass transistor circuits. In Int'l Conj on CAD, pages 663-670, 1997
5. Collaborative Benchmarking Laboratory. 1993 LGSynth Benchmar ks. North Carolina State University, Department of Computer Science, 1993
6. R. Drechsler, N. Drechsler, and W. Gunther. Fast exact minimization of BDDs. IEEE Trans. on CAD, 19(3):384-389, 2000
7. R. Drechsler and W. Gunther. Towards One-Pass Synthesis. Kluwer Academic P ublishers, 2002
8. F. Ferrandi, A. Macii, E. Macii, M. Poncino, R. Scarsi, and F. Somenzi. Symbolic algorithms for layout-oriented synthesis of pass transistor logic circuits. In Int Conj on CAD, pages 235-241, 1998
9. S. Friedman and K. Supowit. Finding the optimal variable ordering for binary decision diagrams. In Design Automation Conj, pages 348-356 ,1 987
10. H. Fujii, G. Ootomo, and C. Hori. Interleaving based variable ordering methods for ordered binary decision diagrams. In Int'/ Conj on CAD, pages 38-41, 1993
11. W. Gunther and R. Drechsler. Improving EAs for Sequencing P roblems. In Genetic and Evolutionary Computation Conference, 175-1 80,2000
12. N. Ishiura, H. Sawada, and S. Yajima. Minimization of binary decision diagrams based on exchange of variables. In Int'[ Conj on CAD, pages 472-475, 1991
13. s.-w. Jeong, T.-S. Kim, and F. Somenzi. An efficient method for optimal BDD ordering computati on. In International Conference on VLSI and CAD. 1993
14. L. Macchiarulo, L. Benini, and E. Macii. On-The-fty layout generation for PTL macrocells. In Design. Automation and Testin Europe, pages 546-551, 2001
15. [15) A. Mukherj ee, R. Sudhakar, M. Marek-Sadowska. and S. Long. Wave steering in YADDs: A novel non-iterative synthesis and layout technique. In Design Automation ConI, pages 466-471,1999
16. [16) R. Rudell. Dynamic variable ordering for ordered binary decision diagrams. In Int'/ Conj on CAD. pages 42-47, 1993
17. [17) F Somenzi. CU Decision Diagram Package Release 2.3.1. University of Colorado at Boulder, 2002
18. c. Yang and M. Ciesielski. BDS: A BDD-based logic optimization system IEEE Trans. on CAD, 21(7):866-876, 2002