Approximation and decomposition of binary decision diagrams

Proceedings - Design Automation Conference

Volumn , Issue , 1998, Pages 445-450

  Ravi, Kavita ^a   McMillan, Kenneth L ^b   Shiple, Thomas R ^c   Somenzi, Fabio ^a  

^a UNIVERSITY OF COLORADO   (United States)

^b CADENCE DESIGN SYSTEMS   (United States)

^c SYNOPSYS INC   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

APPROXIMATION ALGORITHMS; BOOLEAN FUNCTIONS; MODEL CHECKING; ALGORITHMS; APPROXIMATION THEORY; DECISION THEORY; PROBLEM SOLVING;

BINARY DECISION DIAGRAMS (BDDS); DECOMPOSITION ALGORITHM; FORMAL VERIFICATION TOOLS; HARD PROBLEMS; REACHABILITY ANALYSIS;

BINARY DECISION DIAGRAMS; FORMAL LOGIC;

BINARY DECISION DIAGRAMS (BDD); MODEL CHECKING ALGORITHMS;

EID: 0031641253     PISSN: 0738100X     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/277044.277168     Document Type: Conference Paper

References (28)

1. R. K. Brayton et al. VIS: A system for verification and synthesis. In T. Henzinger andR. Alur, editors, Eigth Conference on Computer Aided Verification(CAV'96), pages 428-432. Springer-Verlag, Rutgers University, 1996. LNCS 1102.
2. R. E. Bryant. Graph-based algorithms for boolean function manipulation. IEEE Transactions on Computers, C-35(8):677-691, August 1986.
3. J. R. Burch, E. M. Clarke, and D. E. Long. Representing circuits more efficiently in symbolic model checking. In Proceedings of the Design Automation Conference, pages 403-407, San Francisco, CA, June 1991.
4. J. R. Burch, E. M. Clarke, K. L. McMillan, D. L. Dill, and L. J. Hwang. Symbolic model checking: 1020 states and beyond. In Proceedings of the Fifth Annual Symposium on Logic in Computer Science, June 1990.
5. G. Cabodi, R Camurati, L. Lavagno, and S. Quer, Disjunctive partitionining and partial iterative squaring: An effective approach for symbolic traversal of large circuits. In Proceedings of the Design Automation Conference, pages 728-733, Anaheim, CA, June 1997.
6. G. Cabodi, P. Camurati, and S. Quer. Improved reachability analysis of large finite state machines. In Proceedings of the International Conference on Computer-Aided Design, pages 354-360, Santa Clara, CA, November 1996.
7. H. Cho, G. D. Hachtel, E. Macii, B. Plessier, and F. Somenzi. Algorithms for approximate FSM traversal based on state space decomposition. IEEE Transactions on Computer-Aided Design, 15(12): 1465-1478, December 1996.
8. O. Coudert, C. Berthet, and J. C. Madre. Verification of sequential machines using boolean functional vectors. In L. Claesen, editor, Proceedings IFIP International Workshop on Applied Formal Methods for Correct VLSI Design, pages 111-128, Leuven, Belgium, November 1989.
9. O. Coudert and J. C. Madre. A unified framework for the formal verification of sequential circuits. In Proceedings of the IEEE International Conference on Computer Aided Design, pages 126-129, November 1990.
10. D. Geist and I. Beer. Efficient model checking by automated ordering of transition relation parititons. In D. L. Dill, editor, Sixth Conference on Computer Aided Verification (CAV'94), pages 299-310, Berlin, 1994. Springer-Verlag. LNCS 818.
11. Y. Hong, P. A. Beerel, J. R. Burch, and K. L. McMillan. Safe BDD minimization using don't cares. In Proceedings of the Design Automation Conference, pages 208-213, Anaheim, CA, June 1997.
12. S.-W. Jeong, B. Plessier, G. D. Hachtel, and F. Somenzi. Variable ordering and selection for FSM traversal. In Proceedings of the IEEE International Conference on Computer Aided Design, pages 476-479, Santa Clara, CA, November 1991.
13. R. P. Kurshan. Computer-Aided Verification of Coordinating Processes. Princeton University Press, Princeton, NJ, 1994.
14. R. P. Kurshan. Formal verification in a commercial setting. In Proceedings of the Design Automation Conference, pages 258-262, Anaheim, CA, June 1997.
15. W. Lee, A. Pardo, J. Jang, G. Hachtel, and F. Somenzi. Tearing based abstraction for CTL model checking. In Proceedings of the International Conf erence on Computer-Aided Design, pages 76-81, San Jose, CA, November 1996.
16. D. E. Long. Model Checking, Abstraction, and Compositional Verification. PhD thesis, Carnegie-Mellon University, July 1993.
17. K. L. McMillan. Symbolic Model Checking. Kluwer Academic Publishers, Boston, MA, 1994.
18. K. L. McMillan. A conjunctively decomposed boolean representation for symbolic model checking. In R. Alur and T. A. Henzinger, editors, 8th Conference on Computer Aided Verification (CAV'96), pages 13-25. Springer-Verlag, Berlin, August 1996. LNCS 1102.
19. A. Narayan, A. J. Isles, J. Jain, R. K. Brayton, and A.L. Sangiovanni-Vincentelli. Reachability analysis using partitioned ROBDDs. In Proceedings of the International Conf erence on Computer-Aided Design, pages 388-393, November 1997.
20. A. Narayan, J. Jain, M. Fujita, and A. L. Sangiovanni-Vincentelli. Partition ROBDDs: A compact, canonical and efficiently manipulable representation for boolean functions. In Proceedings of the International Conference on Computer- Aided Design, pages 547-554, Santa Clara, CA, November 1996.
21. A. Pardo and G. D. Hachtel. Automatic abstraction techniques for propositional/x-calculus model checking. In O. Grumberg, editor. Ninth Conference on Computer Aided Verification (CAV'97). Springer-Verlag, Berlin, 1997. LNCS 1254.
22. R. K. Ranjan, A. Aziz, R. K. Brayton, B. F. Plessier, and C. Pixley. Efficient BDD algorithms for FSM synthesis and verification. Presented at IWLS95, Lake Tahoe, CA., May 1995.
23. K. Ravi and F. Somenzi. High-density reachability analysis. In Proceedings of the International Conference on Computer-Aided Design, pages 154-158, San Jose, CA, November 1995.
24. R. Rudell. Dynamic variable ordering for ordered binary decision diagrams. In Proceedings of the International Conference on Computer-Aided Design, pages 42-47, Santa Clara, CA, November 1993.
25. T. R. Shiple. Formal Analysis of Synchronous Circuits. PhD thesis. University of California at Berkeley, Electronics Research Laboratory, College of Engineering, University of California, Berkeley, CA 94720, October 1996. Memorandum No. UCB/ERL M96/76.
26. T. R. Shiple, R. K. Ranjan, A. L. Sangiovanni-Vincentelli, and R. K. Brayton. Deciding state reachability for large FSMs. Technical Report UCB/ERL M97/73, University of California at Berkeley, August 1996.
27. F. Somenzi. CUDD: CU Decision Diagram Package. ftp://vlsi.colorado.edu/pub/.
28. H. Touati, H. Savoj, B. Lin, R. K. Brayton, and A. Sangiovanni-Vincentelli. Implicit enumeration of finite state machines using BDD's. In Proceedings of the IEEE International Conference on Computer Aided Design, pages 130-133, November 1990.