Equivalence checking combining a structural SAT-solver, BDDs, and simulation

Proceedings - IEEE International Conference on Computer Design: VLSI in Computers and Processors

Volumn , Issue , 2000, Pages 459-464

  Paruthi, Viresh ^a   Kuehlmann, Andreas ^a  

^a IBM   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; BOOLEAN FUNCTIONS; COMPUTATIONAL COMPLEXITY; COMPUTER AIDED DESIGN; COMPUTER SIMULATION; EQUIVALENCE CLASSES; MICROPROCESSOR CHIPS;

EQUIVALENCE CHECKING; STRUCTURAL SATISFIABILITY (SAT) SOLVER;

COMBINATORIAL CIRCUITS;

EID: 0033714065     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (17)