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Volumn , Issue , 2001, Pages 546-551

On-the-fly layout generation for PTL macrocells

Author keywords

[No Author keywords available]

Indexed keywords

AUTOMATIC LAYOUT; AUTOMATIC SYNTHESIS; LAYOUT GENERATIONS; PASS TRANSISTORS; PASS-TRANSISTOR LOGIC; PHYSICAL SYNTHESIS; QUALITY OF RESULTS; SEAMLESS INTEGRATION;

EID: 0038450554     PISSN: 15301591     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/DATE.2001.915077     Document Type: Conference Paper
Times cited : (21)

References (16)
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    • Oklobdzija, V.1
  • 2
    • 0032169243 scopus 로고    scopus 로고
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    • T. Kuroda, T. Sakurai, "Low-Power Circuit Design Techniques for Multimedia CMOS VLSls", Electronics and Communications in Japan, Part 3, Vol. 81, No. 9, p. 67-74, 1998.
    • (1998) Electronics and Communications in Japan, Part 3 , vol.81 , Issue.9 , pp. 67-74
    • Kuroda, T.1    Sakurai, T.2
  • 3
    • 0031189144 scopus 로고    scopus 로고
    • Low-power logic styles: CMOS versus pass-transistor logic
    • R. Zimmermann, W. Fichtner, i "Low-Power Logic Styles: CMOS versus Pass-Transistor Logic", IEEE Journal of Solid-State Circuits, Vol. 32, No. 7, pp. 1079, 1997.
    • (1997) IEEE Journal of Solid-State Circuits , vol.32 , Issue.7 , pp. 1079
    • Zimmermann, R.1    Fichtner I, W.2
  • 4
    • 0032218681 scopus 로고    scopus 로고
    • A survey for pass-transistor logic technologies
    • K. Taki, "A Survey for Pass-Transistor Logic Technologies", ASPDAC-98, pp. 223-225, 1998.
    • (1998) ASPDAC-98 , pp. 223-225
    • Taki, K.1
  • 6
    • 0032301257 scopus 로고    scopus 로고
    • Area-oriented synthesis for pass-transistor logic
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    • (1998) ICCD-98 , pp. 160-167
    • Chaudhry, R.1    Liu, T.-H.2    Aziz, A.3    Burns, J.4
  • 9
    • 0032311880 scopus 로고    scopus 로고
    • Symbolic algorithms for layout-oriented synthesis of pass transistor logic circuits
    • F. Ferrandi, A. Macii, E. Macii, M. Poncino, R. Scarsi, F. Somenzi, "Symbolic Algorithms for Layout-Oriented Synthesis of Pass Transistor Logic Circuits", ICCAD-98, pp. 235-241, 1998.
    • (1998) ICCAD-98 , pp. 235-241
    • Ferrandi, F.1    Macii, A.2    Macii, E.3    Poncino, M.4    Scarsi, R.5    Somenzi, F.6
  • 11
    • 0032218679 scopus 로고    scopus 로고
    • ALPS: An automatic layouter for pass-transistor cell synthesis
    • Y. Sasaki, K. Rikino, K. Yano, "ALPS: An Automatic Layouter for Pass-Transistor Cell Synthesis", ASPDAC-98, pp. 227-232, 1998.
    • (1998) ASPDAC-98 , pp. 227-232
    • Sasaki, Y.1    Rikino, K.2    Yano, K.3
  • 12
    • 0032636955 scopus 로고    scopus 로고
    • Transistor level micro-placement and routing for two-dimensional digital vlsi cell synthesis
    • M. A. Riepe, K. A. Sakallah, "Transistor level Micro-Placement and Routing for Two-Dimensional Digital VLSI Cell Synthesis", ISPD-99, pp. 74-81, 1999.
    • (1999) ISPD-99 , pp. 74-81
    • Riepe, M.A.1    Sakallah, K.A.2
  • 13
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    • A neutral netlist of 10 combinational benchmark circuits and a target translator in fortran
    • F. Brglez, H. Fujiwara, "A Neutral Netlist of 10 Combinational Benchmark Circuits and a Target Translator in Fortran", ISCAS-8S, pp. 785-794, 1985.
    • (1985) ISCAS-8S , pp. 785-794
    • Brglez, F.1    Fujiwara, H.2
  • 15
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* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.