On the generation of multiplexer circuits for pass transistor logic

Proceedings -Design, Automation and Test in Europe, DATE

Volumn , Issue , 2000, Pages 372-378

  Scholl, Christoph ^a   Becker, Bernd ^a  

^a UNIVERSITY OF FREIBURG   (Germany)

Author keywords

[No Author keywords available]

Indexed keywords

BDD OPTIMIZATION; DIRECT MAPPING; INPUT VARIABLES; OPTIMIZATION APPROACH; OPTIMIZATION POTENTIAL; ORDER RESTRICTION; PASS TRANSISTORS; PASS-TRANSISTOR LOGIC;

DESIGN; EXHIBITIONS; MULTIPLEXING; MULTIPLEXING EQUIPMENT; OPTIMIZATION;

LOGIC CIRCUITS;

EID: 0001536086     PISSN: 15301591     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/DATE.2000.840298     Document Type: Conference Paper

References (23)

1. P. Ashar, A. Ghosh, and S. Devadas. Boolean satisfiability and equivalence checking using general binary decision diagrams. In Int' l Conf. on CAD, 1991.
2. J. Bern, J. Gergov, C. Meinel, and A. Slobodová. Boolean manipulation with free BDD's. First experimental results. In European Design & Test Conf., pages 200-207, 1994.
3. V. Bertacco, S. Minato, P. Verplaetse, L. Benini, and G. De Micheli. Decision diagrams and pass transistor logic synthesis. In Int' l Workshop on Logic Synth., 1997.
4. K. S. Brace, R. L. Rudell, and R. E. Bryant. Efficient implementation of a BDD package. In Design Automation Conf., pages 40-45, 1990.
5. R. E. Bryant. Graph - based algorithms for Boolean function manipulation. IEEE Trans. on Comp., 35(8):677-691, 1986.
6. P. Buch, A. Narayan, A. R. Newton, and A. L. Sangiovanni-Vincentelli. Logic synthesis for large pass transistor circuits. In Int' l Conf. on CAD, pages 663-670, 1997.
7. S. Chang, D. Cheng, and M. Marek-Sadowska. Minimizing ROBDD size of incompletely specified multiple output functions. In European Design & Test Conf., pages 620-624, 1994.
8. R. Chaudhry, T. -H. Liu, A. Aziz, and J. L. Burns. Areaoriented synthesis for pass-transistor logic. In Int' l Conf. on Comp. Design, pages 160-167, 1998.
9. T. S. Cheung and K. Asada. Regenerative passtransistor logic: A circuit technique for high speed digital design. IEICE Trans. Electron., E79- C(9):1274-1283, 1996.
10. F. Ferrandi, A. Macii, E. Macii, M. Poncino, R. Scarsi, and F. Somenzi. Symbolic algorithms for layoutoriented synthesis of pass transistor logic circuits. In Int' l Conf. on CAD, 1998.
11. K. Karplus. ITEM: an if-then-else minimizer for logic synthesis. Technical report, University of California, Santa Cruz, 1992.
12. F. S. Lai and W. Hwang. Design and implementation of differential cascode voltage switch with pass-gate (dcvspg) logic for high-performance digital systems. IEEE Jour. of Solid-State Circ., 32(4):563-573, April 1997.
13. T. -H. Liu, A. Aziz, and J. L. Burns. Performance driven synthesis for pass-transistor logic. In Int' l Workshop on Logic Synth., pages 255-259, 1998.
14. D. E. Long. BDD library. 1993.
15. A. Parameswar, H. Hara, and T. Sakurai. A high speed, low power, swing restored pass-transistor logic based multiply and accumulate circuit for multimedia applications. In Proc. Custom Integrated Circuits Conf., pages 278-281, May 1994.
16. R. Rudell. Dynamic variable ordering for ordered binary decision diagrams. In Int' l Conf. on CAD, pages 42-47, 1993.
17. C. Scholl, S. Melchior, G. Hotz, and P. Molitor. Minimizing ROBDD sizes of incompletely specified functions by exploiting strong symmetries. In European Design & Test Conf., pages 229-234, 1997.
18. E. Sentovich, K. Singh, L. Lavagno, Ch. Moon, R. Murgai, A. Saldanha, H. Savoj, P. Stephan, R. Brayton, and A. Sangiovanni-Vincentelli. SIS: A system for sequential circuit synthesis. Technical report, University of Berkeley, 1992.
19. T. R. Shiple, R. Hojati, A. L. Sangiovanni-Vincentelli, and R. K. Brayton. Heuristic minimization of BDDs using don' t cares. In Design Automation Conf., pages 225-231, 1994.
20. F. Somenzi. CUDD: CU Decision Diagram Package Release 2. 3. 0. University of Colorado at Boulder, 1998.
21. N. Weste and K. Eshraghian. Principles of CMOS VLSI Design: A Systems Perspective. Addison- Wesley, 1992.
22. K. Yano, Y. Sasaki, K. Rikino, and K. Seki. Top-down pass-transistor logic design. IEEE Jour. of Solid-State Circ., 31(6):792-803, June 1996.
23. K. Yano, T. Yamanaka, T. Nishida, and M. Satio. A 3.8-ns CMOS 16 + 16-b multiplier using complementary pass-transistor logic. IEEE Jour. of Solid-State Circ., 25(2):388-395, April 1990.