Symbolic algorithms for layout-oriented synthesis of pass transistor logic circuits

IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers

Volumn , Issue , 1998, Pages 235-240

  Ferrandi, F ^a   Macii, A ^a   Macii, E ^a   Poncino, M ^a   Scarsi, R ^a   Somenzi, F ^a  

^a POLITECNICO DI MILANO   (Italy)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; ELECTRIC NETWORK SYNTHESIS; INTEGRATED CIRCUIT LAYOUT; LOGIC CIRCUITS; MATHEMATICAL MODELS; TRANSISTORS;

PASS TRANSISTOR LOGIC CIRCUITS (PTL); SYMBOLIC ALGORITHMS;

COMPUTER AIDED LOGIC DESIGN;

EID: 0032311880     PISSN: 10923152     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/288548.288619     Document Type: Conference Paper

References (14)