Testing with decision diagrams

Integration, the VLSI Journal

Volumn 26, Issue 1-2, 1998, Pages 5-20

  Becker, Bernd ^a  

^a UNIVERSITY OF FREIBURG   (Germany)

Author keywords

Buit in self test; Decision diagrams; Fault detection; Synchronization; Synthesis for testability

Indexed keywords

ALGORITHMS; BUILT-IN SELF TEST; COMPUTATIONAL METHODS; COMPUTER AIDED DESIGN; DECISION THEORY; ELECTRIC FAULT LOCATION; ELECTRIC NETWORK ANALYSIS; ELECTRIC NETWORK SYNTHESIS; INTEGRATED CIRCUIT TESTING; MATHEMATICAL MODELS; MATRIX ALGEBRA; SYNCHRONIZATION;

DECISION DIAGRAMS (DD); SYNTHESIS FOR TESTABILITY (SFT);

VLSI CIRCUITS;

EID: 0032308363     PISSN: 01679260     EISSN: None     Source Type: Journal    
DOI: 10.1016/S0167-9260(98)00018-2     Document Type: Article

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