Dynamic QoS management for chip multiprocessors

Transactions on Architecture and Code Optimization

Volumn 9, Issue 3, 2012, Pages

  Li, Bin ^a   Peh, Li Shiuan ^b   Zhao, Li ^a   Iyer, Ravi ^a  

^a INTEL CORPORATION   (United States)

^b Department of Electrical Engineering and Computer Science   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CHIP MULTIPROCESSOR; CHIP MULTIPROCESSORS; DYNAMIC QOS MANAGEMENT; DYNAMIC RESOURCE MANAGEMENT; EVALUATION RESULTS; FEEDBACK CONTROLLER; MEMORY RESOURCES; MODERN HIGH PERFORMANCE; NETWORK ON CHIP; OFF-CHIP MEMORIES; PROPORTIONAL-INTEGRAL; QOS MANAGEMENT; RESOURCE MANAGEMENT POLICY; RESOURCE SHARING; RESOURCE USAGE; RUNTIMES; SEMICONDUCTOR TECHNOLOGY; SHARED RESOURCES;

COMPUTER ARCHITECTURE; MICROPROCESSOR CHIPS; NATURAL RESOURCES MANAGEMENT; RESOURCE ALLOCATION; SEMICONDUCTOR DEVICE MANUFACTURE; SYSTEMS ANALYSIS; VLSI CIRCUITS;

QUALITY OF SERVICE;

EID: 84870209080     PISSN: 15443566     EISSN: 15443973     Source Type: Journal    
DOI: 10.1145/2355585.2355590     Document Type: Article

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