Application-aware prioritization mechanisms for on-chip networks

Proceedings of the Annual International Symposium on Microarchitecture, MICRO

Volumn , Issue , 2009, Pages 280-291

  Das, Reetuparna ^a   Mutlu, Onur ^b   Moscibroda, Thomas ^c   Das, Chita R ^a  

^a PENNSYLVANIA STATE UNIVERSITY   (United States)

^b CARNEGIE MELLON UNIVERSITY   (United States)

^c MICROSOFT RESEARCH   (United States)

Author keywords

Arbitration; Memory systems; Multi core; On chip networks; Packet scheduling; Prioritization

Indexed keywords

MEMORY SYSTEMS; MULTI CORE; ON-CHIP NETWORKS; PACKET SCHEDULING; PRIORITIZATION;

CRITICALITY (NUCLEAR FISSION); MICROPROCESSOR CHIPS; MULTIPROGRAMMING; PACKET NETWORKS; SCHEDULING;

ROUTERS;

EID: 76749124429     PISSN: 10724451     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/1669112.1669150     Document Type: Conference Paper

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