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Volumn 71, Issue 5, 2011, Pages 700-713

CoQoS: Coordinating QoS-aware shared resources in NoC-based SoCs

Author keywords

Memory architecture; Network on chip; Quality of service; Resource management; System on chip

Indexed keywords

CLASS OF SERVICE; CRITICAL RESOURCES; IP BLOCK; MULTIPLE QOS; MULTIPLE RESOURCES; NETWORK-ON-CHIP; OPEN PROBLEMS; PROGRAMMABLE CORES; QOS ARCHITECTURE; QOS SUPPORT; RESOURCE MANAGEMENT; RESOURCE SHARING; SHARED RESOURCES; SOC ARCHITECTURE; SOC PLATFORMS; SYSTEM ON CHIPS;

EID: 79953203158     PISSN: 07437315     EISSN: None     Source Type: Journal    
DOI: 10.1016/j.jpdc.2010.10.013     Document Type: Article
Times cited : (36)

References (49)
  • 4
    • 79953203644 scopus 로고    scopus 로고
    • Intel Atom Processor, 2008. http://www.intel.com/technology/atom/.
    • (2008) Intel Atom Processor
  • 6
    • 27344444925 scopus 로고    scopus 로고
    • A router architecture for connection-oriented service guarantees in the MANGO clockless network-on-chip
    • DOI 10.1109/DATE.2005.36, 1395761, Proceedings - Design, Automation and Test in Europe, DATE '05
    • T. Bjerregaard, and J. Sparso A router architecture for connection-oriented service guarantees in the MANGO clockless network-on-chip Proceedings of the Conference on Design, Automation and Test in Europe vol. 2 2005 IEEE Computer Society 1226 1231 (Pubitemid 44172177)
    • (2005) Proceedings -Design, Automation and Test in Europe, DATE '05 , vol.2 , pp. 1226-1231
    • Bjerregaard, T.1    Sparso, J.2
  • 8
    • 21244474546 scopus 로고    scopus 로고
    • Predicting inter-thread cache contention on a chip multi-processor architecture
    • Proceedings - 11th International Symposium on High-Performance Computer Architecture, HPCA-11 2005
    • D. Chandra, F. Guo, S. Kim, and Y. Solihin Predicting inter-thread cache contention on a chip multiprocessor architecture Proceedings of the 11th International Symposium on High-Performance Computer Architecture 2005 IEEE Computer Society Washington, DC, USA 340 351 (Pubitemid 41731513)
    • (2005) Proceedings - International Symposium on High-Performance Computer Architecture , pp. 340-351
    • Chandra, D.1    Guo, F.2    Kim, S.3    Solihin, Y.4
  • 9
    • 79953186536 scopus 로고    scopus 로고
    • ARM Cortex-A9 MPCore, 2007. http://www.arm.com/products/CPUs/ARMCortex- A9MPCore.html.
    • (2007) ARM Cortex-A9 MPCore
  • 13
    • 14844314436 scopus 로고    scopus 로고
    • An asynchronous on-chip network router with Quality-of-Service (QoS) support
    • TB3.3, Proceedings - IEEE International SOC Conference
    • T. Felicijan, and S.B. Furber An asynchronous on-chip network router with quality-of-service (QoS) support Proceedings of IEEE International SoC Conference 2004 IEEE Computer Society 274 277 (Pubitemid 40338417)
    • (2004) Proceedings - IEEE International SOC Conference , pp. 274-277
    • Felicijan, T.1    Furber, S.B.2
  • 14
    • 27344456043 scopus 로고    scopus 로고
    • Æthereal network on chip: Concepts, architectures, and implementations
    • DOI 10.1109/MDT.2005.99
    • K. Goossens, J. Dielissen, and A. Radulescu Æthereal network on chip: concepts, architectures, and implementations Design and Test of Computers, IEEE 22 2005 414 421 (Pubitemid 41522729)
    • (2005) IEEE Design and Test of Computers , vol.22 , Issue.5 , pp. 414-421
    • Goossens, K.1    Dielissen, J.2    Radulescu, A.3
  • 19
    • 79953165426 scopus 로고    scopus 로고
    • Apple Corporation, 2007. http://www.apple.com/iphone/.
    • (2007) Apple Corporation
  • 21
    • 36349002905 scopus 로고    scopus 로고
    • QoS policies and architecture for cache/memory in CMP platforms
    • DOI 10.1145/1269899.1254886, SIGMETRICS'07 - Proceedings of the 2007 International Conference on Measurement and Modeling of Computer Systems
    • R. Iyer, L. Zhao, F. Guo, R. Illikkal, S. Makineni, D. Newell, Y. Solihin, L. Hsu, and S. Reinhardt QoS policies and architecture for cache/memory in CMP platforms Proceedings of the ACM SIGMETRICS Conference vol. 35 2007 ACM 25 36 (Pubitemid 350158070)
    • (2007) Performance Evaluation Review , vol.35 , Issue.1 , pp. 25-36
    • Iyer, R.1    Zhao, L.2    Guo, F.3    Illikkal, R.4    Makineni, S.5    Newell, D.6    Solihin, Y.7    Hsu, L.8    Reinhardt, S.9
  • 22
    • 70350060187 scopus 로고    scopus 로고
    • ORION 2.0: A fast and accurate NoC power and area model for early-stage design space exploration
    • IEEE Computer Society Nice, France
    • A. Kahng, B. Li, L.S. Peh, and K. Samadi ORION 2.0: a fast and accurate NoC power and area model for early-stage design space exploration Proceedings of Design Automation and Test in Europe, DATE 2009 IEEE Computer Society Nice, France 423 428
    • (2009) Proceedings of Design Automation and Test in Europe, DATE , pp. 423-428
    • Kahng, A.1    Li, B.2    Peh, L.S.3    Samadi, K.4
  • 28
    • 3042740415 scopus 로고    scopus 로고
    • Guaranteed bandwidth using looped containers in temporally disjoint networks within the Nostrum network on chip
    • IEEE Computer Society
    • M. Millberg, E. Nilsson, R. Thid, and A. Jantsch Guaranteed bandwidth using looped containers in temporally disjoint networks within the Nostrum network on chip Proceedings of the Conference on Design, Automation and Test in Europe Vol. 2 2004 IEEE Computer Society 890 895
    • (2004) Proceedings of the Conference on Design, Automation and Test in Europe , vol.2 , pp. 890-895
    • Millberg, M.1    Nilsson, E.2    Thid, R.3    Jantsch, A.4
  • 34
    • 35348816719 scopus 로고    scopus 로고
    • Virtual private caches
    • DOI 10.1145/1250662.1250671, ISCA'07: 34th Annual International Symposium on Computer Architecture, Conference Proceedings
    • K.J. Nesbit, J. Laudon, and J.E. Smith Virtual private caches Proceedings of the 34th Annual International Symposium on Computer Architecture 2007 IEEE Computer Society San Diego, California, USA 57 68 (Pubitemid 47582091)
    • (2007) Proceedings - International Symposium on Computer Architecture , pp. 57-68
    • Nesbit, K.J.1    Laudon, J.2    Smith, J.E.3
  • 36
    • 34548042910 scopus 로고    scopus 로고
    • Utility-based cache partitioning: A low-overhead, high-performance, runtime mechanism to partition shared caches
    • DOI 10.1109/MICRO.2006.49, 4041865, Proceedings of the 39th Annual IEEE/ACM International Symposium on Microarchitecture, MICRO-39
    • M.K. Qureshi, and Y.N. Patt Utility-based cache partitioning: a low-overhead, high-performance, runtime mechanism to partition shared caches Proceedings of the 39th Annual IEEE/ACM International Symposium on Microarchitecture 2006 IEEE Computer Society 423 432 (Pubitemid 351337015)
    • (2006) Proceedings of the Annual International Symposium on Microarchitecture, MICRO , pp. 423-432
    • Qureshi, M.K.1    Patt, Y.N.2
  • 37
    • 34247108325 scopus 로고    scopus 로고
    • Architectural support for operating system-driven CMP cache management
    • DOI 10.1145/1152154.1152160, PACT 2006 - Proceedings of the Fifteenth International Conference on Parallel Architectures and Compilation Techniques
    • N. Rafique, W.T. Lim, and M. Thottethodi Architectural support for operating system-driven CMP cache management Proceedings of the 15th International Conference on Parallel Architectures and Compilation Techniques 2006 ACM 2 12 (Pubitemid 46601076)
    • (2006) Parallel Architectures and Compilation Techniques - Conference Proceedings, PACT , vol.2006 , pp. 2-12
    • Rafique, N.1    Lim, W.-T.2    Thottethodi, M.3
  • 39
    • 1342323879 scopus 로고    scopus 로고
    • Dpr, lpr: Proactive resource allocation algorithms for asynchronous real-time distributed systems
    • B. Ravindran, and P. Li Dpr, lpr: proactive resource allocation algorithms for asynchronous real-time distributed systems IEEE Trans. Comput. 53 2004 201 216
    • (2004) IEEE Trans. Comput. , vol.53 , pp. 201-216
    • Ravindran, B.1    Li, P.2
  • 46
    • 27344447802 scopus 로고    scopus 로고
    • A quality-of-service mechanism for interconnection networks in system-on-chips
    • DOI 10.1109/DATE.2005.33, 1395762, Proceedings - Design, Automation and Test in Europe, DATE '05
    • W.D. Weber, J. Chou, I. Swarbrick, and D. Wingard A quality-of-service mechanism for interconnection networks in system-on-chips Proceedings of the conference on Design, Automation and Test in Europe vol. 2 2005 IEEE Computer Society 1232 1237 (Pubitemid 44172178)
    • (2005) Proceedings -Design, Automation and Test in Europe, DATE '05 , vol.2 , pp. 1232-1237
    • Weber, W.-D.1    Chou, J.2    Swarbrick, I.3    Wingard, D.4
  • 48
    • 78650754462 scopus 로고    scopus 로고
    • Hardware execution throttling for multi-core resource management
    • X. Zhang, S. Dwarkadas, K. Shen, Hardware execution throttling for multi-core resource management, in: USENIX'09.
    • USENIX'09
    • Zhang, X.1    Dwarkadas, S.2    Shen, K.3
  • 49
    • 4544353204 scopus 로고    scopus 로고
    • Harmonic proportional bandwidth allocation and scheduling for service differentiation on streaming servers
    • X. Zhou, and C.Z. Xu Harmonic proportional bandwidth allocation and scheduling for service differentiation on streaming servers IEEE Trans. Parallel Distrib. Syst. 15 2004 835 848
    • (2004) IEEE Trans. Parallel Distrib. Syst. , vol.15 , pp. 835-848
    • Zhou, X.1    Xu, C.Z.2


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.