Fairness via source throttling: A configurable and high-performance fairness substrate for multi-core memory systems

International Conference on Architectural Support for Programming Languages and Operating Systems - ASPLOS

Volumn , Issue , 2010, Pages 335-346

  Ebrahimi, Eiman ^a   Lee, Chang Joo ^a   Mutlu, Onur ^b   Patt, Yale N ^a  

^a The University of Texas at Austin   (United States)

^b CARNEGIE MELLON UNIVERSITY   (United States)

Author keywords

Fairness; Multi core systems; Shared memory systems; System performance

Indexed keywords

CHIP-MULTIPROCESSOR; CONFIGURABLE; FAIRNESS CONTROL; HARDWARE RESOURCES; LOSS OF PERFORMANCE; MEMORY CONTROLLER; MEMORY SUBSYSTEMS; MEMORY SYSTEMS; MULTI CORE; MULTI-CORE SYSTEMS; NEW APPROACHES; PERFORMANCE TRADE-OFF; RESOURCE SHARING; SHARED CACHE; SHARED MEMORY SYSTEM; SYSTEM FAIRNESS; SYSTEM SOFTWARES;

COMPUTER OPERATING SYSTEMS; LINGUISTICS; MICROPROCESSOR CHIPS;

CACHE MEMORY;

EID: 77952285828     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/1736020.1736058     Document Type: Conference Paper

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