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Volumn , Issue , 2004, Pages 433-443

Predictable performance in SMT processors

Author keywords

ILP; Multithreading; Operating Systems; Performance Predictability; Real Time; SMT; Thread level parallelism

Indexed keywords

COMPUTER ARCHITECTURE; COMPUTER HARDWARE; COMPUTER SYSTEMS; PROGRAM PROCESSORS; QUALITY OF SERVICE; REAL TIME SYSTEMS; RESOURCE ALLOCATION; SURFACE MOUNT TECHNOLOGY;

EID: 4143087192     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/977091.977152     Document Type: Conference Paper
Times cited : (19)

References (25)
  • 1
    • 4143085072 scopus 로고    scopus 로고
    • Will microprocessors become simpler?
    • Nov.
    • D. Alpert. Will microprocessors become simpler? Microprocessor Report, Nov. 2003.
    • (2003) Microprocessor Report
    • Alpert, D.1
  • 10
    • 4143116894 scopus 로고    scopus 로고
    • Contention on 2nd level cache may limit the effectiveness of simultaneous multithreading
    • IRISA, Feb.
    • S. Hily and A. Seznec. Contention on 2nd level cache may limit the effectiveness of simultaneous multithreading. Technical Report 1086, IRISA, Feb. 1997.
    • (1997) Technical Report , vol.1086
    • Hily, S.1    Seznec, A.2


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.