-
1
-
-
4143085072
-
Will microprocessors become simpler?
-
Nov.
-
D. Alpert. Will microprocessors become simpler? Microprocessor Report, Nov. 2003.
-
(2003)
Microprocessor Report
-
-
Alpert, D.1
-
10
-
-
4143116894
-
Contention on 2nd level cache may limit the effectiveness of simultaneous multithreading
-
IRISA, Feb.
-
S. Hily and A. Seznec. Contention on 2nd level cache may limit the effectiveness of simultaneous multithreading. Technical Report 1086, IRISA, Feb. 1997.
-
(1997)
Technical Report
, vol.1086
-
-
Hily, S.1
Seznec, A.2
-
11
-
-
0026869325
-
An elementary processor architecture with simultaneous instruction issuing from multiple threads
-
May
-
H. Hirata, K. Kimura, S. Nagamine, Y. Mochizuki, A. Nishimura, Y. Nakase, and T. Nishizawa. An elementary processor architecture with simultaneous instruction issuing from multiple threads. Proceedings of the 19th Annual Intl. Symposium on Computer Architecture, pages 136-145, May 1992.
-
(1992)
Proceedings of the 19th Annual Intl. Symposium on Computer Architecture
, pp. 136-145
-
-
Hirata, H.1
Kimura, K.2
Nagamine, S.3
Mochizuki, Y.4
Nishimura, A.5
Nakase, Y.6
Nishizawa, T.7
-
14
-
-
4143085069
-
Branch classification for SMT fetch gating
-
P. Knijnenburg, A. Ramirez, J. Larriba, and M. Valero. Branch classification for SMT fetch gating. Proceedings of the 6th Workshop on Multithreaded Execution, Architecture, and Compilation, pages 49-56, 2002.
-
(2002)
Proceedings of the 6th Workshop on Multithreaded Execution, Architecture, and Compilation
, pp. 49-56
-
-
Knijnenburg, P.1
Ramirez, A.2
Larriba, J.3
Valero, M.4
-
15
-
-
0034825813
-
Improving 3D geometry transformations on a simultaneous multithreaded SIMD processor
-
May
-
C. Limousin, J. Sebot, A. Vartanian, and N. Drach-Temam. Improving 3D geometry transformations on a simultaneous multithreaded SIMD processor. Proceedings of the 15th Intl. Conference on Supercomputing, pages 236-245, May 2001.
-
(2001)
Proceedings of the 15th Intl. Conference on Supercomputing
, pp. 236-245
-
-
Limousin, C.1
Sebot, J.2
Vartanian, A.3
Drach-Temam, N.4
-
17
-
-
0001087280
-
Hyper-threading technology architecture and microarchitecture
-
Feb.
-
D. T. Marr, F. Binns, D. Hill, G. Hinton, D. Koufaty, J. A. Miller, and M. Upton. Hyper-threading technology architecture and microarchitecture. Intel Technology Journal, 6(1), Feb. 2002.
-
(2002)
Intel Technology Journal
, vol.6
, Issue.1
-
-
Marr, D.T.1
Binns, F.2
Hill, D.3
Hinton, G.4
Koufaty, D.5
Miller, J.A.6
Upton, M.7
-
22
-
-
0029666641
-
Exploiting choice: Instruction fetch and issue on an implementable simultaneous multithreading processor
-
Apr.
-
D. Tullsen, S. Eggers, J. Emer, H. Levy, J. Lo, and R. Stamm. Exploiting choice: Instruction fetch and issue on an implementable simultaneous multithreading processor. Proceedings of the 23th Annual Intl. Symposium on Computer Architecture, pages 191-202, Apr. 1996.
-
(1996)
Proceedings of the 23th Annual Intl. Symposium on Computer Architecture
, pp. 191-202
-
-
Tullsen, D.1
Eggers, S.2
Emer, J.3
Levy, H.4
Lo, J.5
Stamm, R.6
-
24
-
-
0038346244
-
SMARTS: Accelerating microarchitecture simulation via rigorous statistical sampling
-
June
-
R. E. Wunderlich, T. F. Wenisch, B. Falsafi, and J. C. Hoe. SMARTS: accelerating microarchitecture simulation via rigorous statistical sampling. Proceedings of the 30th Annual Intl. Symposium on Computer Architecture, pages 84-97, June 2003.
-
(2003)
Proceedings of the 30th Annual Intl. Symposium on Computer Architecture
, pp. 84-97
-
-
Wunderlich, R.E.1
Wenisch, T.F.2
Falsafi, B.3
Hoe, J.C.4
|