-
1
-
-
38849092036
-
-
B. Akessom et al. Real-Time Scheduling of Hybrid Systems using Credit-Controlled Static-Priority Arbitration. Technical report, NXP Semiconductors, 2007. NXP-R-TN 2007/00119.
-
B. Akessom et al. Real-Time Scheduling of Hybrid Systems using Credit-Controlled Static-Priority Arbitration. Technical report, NXP Semiconductors, 2007. NXP-R-TN 2007/00119.
-
-
-
-
3
-
-
0026000660
-
A calculus for network delay. I. Network elements in isolation
-
R. Cruz. A calculus for network delay. I. Network elements in isolation. IEEE Trans. on Info. Theory, 37(1), 1991.
-
(1991)
IEEE Trans. on Info. Theory
, vol.37
, Issue.1
-
-
Cruz, R.1
-
4
-
-
0035444259
-
Viper: A multiprocessor SOC for advanced set-top box and digital TV systems
-
S. Dutta et al. Viper: A multiprocessor SOC for advanced set-top box and digital TV systems. IEEE Design and Test of Computers, 2001.
-
(2001)
IEEE Design and Test of Computers
-
-
Dutta, S.1
-
5
-
-
11844302406
-
Interconnect and memory organization, in SOCs for advanced set-top bones and TV - Evolution, analysis, and trends
-
Kluwer
-
K. Goossens et al. Interconnect and memory organization, in SOCs for advanced set-top bones and TV - Evolution, analysis, and trends. In Interconnect-Centric Design for Advanced SoC and NoC. Kluwer, 2004.
-
(2004)
Interconnect-Centric Design for Advanced SoC and
-
-
Goossens, K.1
-
6
-
-
27344456043
-
The Æthereal network on chip: Concepts, architectures, and implementations
-
K. Goossens et al. The Æthereal network on chip: Concepts, architectures, and implementations. IEEE Design and Test of Computers, 22(5), 2005.
-
(2005)
IEEE Design and Test of Computers
, vol.22
, Issue.5
-
-
Goossens, K.1
-
10
-
-
38849156291
-
-
JEDEC Solid State Technology Association, JESD79-2C edition, May
-
JEDEC Solid State Technology Association. DDR2 SDRAM Specification, JESD79-2C edition, May 2006.
-
(2006)
DDR2 SDRAM Specification
-
-
-
14
-
-
11844249902
-
An efficient on-chip network interface offering guaranteed services, shared-memory abstraction, and flexible network programming
-
A. Rǎdulescu et al. An efficient on-chip network interface offering guaranteed services, shared-memory abstraction, and flexible network programming. IEEE Trans. on CAD of Int. Circ. and Syst., 24(1), 2005.
-
(2005)
IEEE Trans. on CAD of Int. Circ. and Syst
, vol.24
, Issue.1
-
-
Rǎdulescu, A.1
-
16
-
-
0032182533
-
Latency-rate servers: A general model for analysis of traffic scheduling algorithms
-
D. Stiliadis and A. Varma. Latency-rate servers: a general model for analysis of traffic scheduling algorithms. IEEE/ACM Trans. Netw., 6(5), 1998.
-
(1998)
IEEE/ACM Trans. Netw
, vol.6
, Issue.5
-
-
Stiliadis, D.1
Varma, A.2
-
18
-
-
38849115039
-
-
W.-D. Weber. Efficient Shared DRAM Subsystems for SOCs. Sonics, Inc, 2001. White paper.
-
W.-D. Weber. Efficient Shared DRAM Subsystems for SOCs. Sonics, Inc, 2001. White paper.
-
-
-
-
19
-
-
38849125514
-
-
Master's thesis, University of Twente, Jan
-
L. Woltjer. Optimal DDR controller. Master's thesis, University of Twente, Jan. 2005.
-
(2005)
Optimal DDR controller
-
-
Woltjer, L.1
-
20
-
-
0029388337
-
Service disciplines for guaranteed performance service in packet-switching networks
-
H. Zhang. Service disciplines for guaranteed performance service in packet-switching networks. Proceedings of the IEEE, 83(10), 1995.
-
(1995)
Proceedings of the IEEE
, vol.83
, Issue.10
-
-
Zhang, H.1
|