Predator: A predictable SDRAM memory controller

CODES+ISSS 2007: International Conference on Hardware/Software Codesign and System Synthesis

Volumn , Issue , 2007, Pages 251-256

  Akesson, Benny ^a   Goossens, Kees ^b   Ringhofer, Markus ^c  

^a EINDHOVEN UNIVERSITY OF TECHNOLOGY   (Netherlands)

^b DELFT UNIVERSITY OF TECHNOLOGY   (Netherlands)

^c GRAZ UNIVERSITY OF TECHNOLOGY   (Austria)

Author keywords

Memory controller; Predictability; SDRAM; System on chip

Indexed keywords

ACCESS CONTROL; BANDWIDTH; CONTROL EQUIPMENT; INTELLECTUAL PROPERTY; INTERFACES (COMPUTER); MULTIPROCESSING SYSTEMS;

MEMORY CONTROLLER; SDRAM; SYSTEM-ON-CHIP;

RANDOM ACCESS STORAGE;

EID: 38849203001     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/1289816.1289877     Document Type: Conference Paper

References (20)

1. B. Akessom et al. Real-Time Scheduling of Hybrid Systems using Credit-Controlled Static-Priority Arbitration. Technical report, NXP Semiconductors, 2007. NXP-R-TN 2007/00119.
2. A. Burchard et al. A real-time streaming memory controller. In Proc. Design, Automation and Test in Europe Conference and Exhibition (DATE), 2005.
3. R. Cruz. A calculus for network delay. I. Network elements in isolation. IEEE Trans. on Info. Theory, 37(1), 1991.
4. S. Dutta et al. Viper: A multiprocessor SOC for advanced set-top box and digital TV systems. IEEE Design and Test of Computers, 2001.
5. K. Goossens et al. Interconnect and memory organization, in SOCs for advanced set-top bones and TV - Evolution, analysis, and trends. In Interconnect-Centric Design for Advanced SoC and NoC. Kluwer, 2004.
6. K. Goossens et al. The Æthereal network on chip: Concepts, architectures, and implementations. IEEE Design and Test of Computers, 22(5), 2005.
7. A. Hansson and K. Goossens. Trade-offs in the configuration of a network on chip for multiple use-cases. In The 1st ACM/IEEE International Symposium on Networks-on-Chip, 2007.
8. A. Hansson et al. Undisrupted quality-of-service during reconfiguration of multiple applications in networks on chip. In Proc. Design, Automation and Test in Europe Conference and Exhibition (DATE), 2007.
9. S. Heithecker and R. Ernst. Traffic shaping for an FPGA based SDRAM controller with complex QoS requirements. In DAC '05: Proceedings of the 42nd annual conference on Design automation, 2005.
10. JEDEC Solid State Technology Association. DDR2 SDRAM Specification, JESD79-2C edition, May 2006.
11. T.-C. Lin et al. Quality-aware memory controller for multimedia platform SoC. In IEEE Workshop on Signal Processing Systems, SIPS 2003, 2003.
12. C. Macian et al. Beyond performance: Secure and fair memory management for multiple systems on a chip. In IEEE International Conference on Field-Programmable Technology (FPT), 2003.
13. S. Rixner et al. Memory access scheduling. In. ISCA '00: Proceedings of the 27th annual international symposium on Computer architecture, 2000.
14. A. Rǎdulescu et al. An efficient on-chip network interface offering guaranteed services, shared-memory abstraction, and flexible network programming. IEEE Trans. on CAD of Int. Circ. and Syst., 24(1), 2005.
15. F. Steenhof, et al. Networks on chips for high-end consumer-electronics TV system architectures. In Proc. Design, Automation and Test in Europe Conference and Exhibition (DATE), 2006.
16. D. Stiliadis and A. Varma. Latency-rate servers: a general model for analysis of traffic scheduling algorithms. IEEE/ACM Trans. Netw., 6(5), 1998.
17. J.-W. van de Waerdt et al. The TM3270 media-processor. In MICRO 38: Proceedings of the 38th annual IEEE/ACM International Symposium on Microarchitecture, 2005.
18. W.-D. Weber. Efficient Shared DRAM Subsystems for SOCs. Sonics, Inc, 2001. White paper.
19. L. Woltjer. Optimal DDR controller. Master's thesis, University of Twente, Jan. 2005.
20. H. Zhang. Service disciplines for guaranteed performance service in packet-switching networks. Proceedings of the IEEE, 83(10), 1995.