Kilo-NOC: A heterogeneous network-on-chip architecture for scalability and service guarantees

Proceedings - International Symposium on Computer Architecture

Volumn , Issue , 2011, Pages 401-412

  Grot, Boris ^a   Hestness, Joel ^a   Keckler, Stephen W ^a,b   Mutlu, Onur ^c  

^a UNIVERSITY OF TEXAS AT AUSTIN   (United States)

^b NVIDIA   (United States)

^c CARNEGIE MELLON UNIVERSITY   (United States)

Author keywords

Design; Measurement; Performance

Indexed keywords

CHIP-LEVEL; CONNECTED COMPONENT; CONTROL MECHANISM; ELASTIC BUFFER; ENERGY COST; HARDWARE SUPPORTS; NETWORK NODE; NETWORK-ON-CHIP ARCHITECTURES; NETWORKS ON CHIPS; PERFORMANCE; QOS SUPPORT; SERVICE GUARANTEES; TOPOLOGY AWARE; NETWORK AREA; QOS ARCHITECTURE;

COMPUTER ARCHITECTURE; COST BENEFIT ANALYSIS; ENERGY EFFICIENCY; FLOW CONTROL; HETEROGENEOUS NETWORKS; QUALITY OF SERVICE; ROUTERS; VLSI CIRCUITS; DESIGN; MEASUREMENTS; NETWORK ARCHITECTURE;

NETWORK ARCHITECTURE; COST BENEFIT ANALYSIS;

EID: 80052522708     PISSN: 10636897     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/2000064.2000112     Document Type: Conference Paper

References (31)

1. J. D. Balfour and W. J. Dally. Design Tradeoffs for Tiled CMP On-chip Networks. In International Conference on Supercomputing, pages 187-198, June 2006.
2. C. Bienia, S. Kumar, J. P. Singh, and K. Li. The PARSEC Benchmark Suite: Characterization and Architectural Implications. In International Conference on Parallel Architectures and Compilation Techniques, pages 72-81, October 2008.
3. N. L. Binkert, R. G. Dreslinski, L. R. Hsu, K. T. Lim, A. G. Saidi, and S. K. Reinhardt. The M5 Simulator: Modeling Networked Systems. IEEE Micro, 26(4):52-60, July/August 2006.
4. W. J. Dally. Virtual-channel Flow Control. In International Symposium on Computer Architecture, pages 60-68, June 1990.
5. W. J. Dally and B. Towles. Route Packets, Not Wires: On-chip Interconnection Networks. In International Conference on Design Automation, pages 684-689, June 2001.
6. W. J. Dally and B. Towles. Principles and Practices of Interconnection Networks. Morgan Kaufmann Publishers Inc., San Francisco, CA, USA, 2004.
7. A. Demers, S. Keshav, and S. Shenker. Analysis and Simulation of a Fair Queueing Algorithm. In Symposium Proceedings on Communications Architectures and Protocols (SIGCOMM), pages 1-12, September 1989.
8. P. Gratz, C. Kim, K. Sankaralingam, H. Hanson, P. Shivakumar, S. W. Keckler, and D. Burger. On-Chip Interconnection Networks of the TRIPS Chip. IEEE Micro, 27(5):41-50, September/October 2007.
9. B. Grot, J. Hestness, S. W. Keckler, and O. Mutlu. Express Cube Topologies for on-Chip Interconnects. In International Symposium on High-Performance Computer Architecture, pages 163-174, February 2009.
10. B. Grot, S. W. Keckler, and O. Mutlu. Preemptive Virtual Clock: a Flexible, Efficient, and Cost-effective QOS Scheme for Networks-on-Chip. In International Symposium on Microarchitecture, pages 268-279, December 2009.
11. J. Hestness, B. Grot, and S. W. Keckler. Netrace: Dependency-driven Trace-based Network-on-Chip Simulation. In Workshop on Network on Chip Architectures, pages 31-36, December 2010.
12. International Technology Roadmap for Semiconductors. http://www.itrs.net/ links/2009ITRS/Home2009.htm,2009.
13. A. Kahng, B. Li, L.-S. Peh, and K. Samadi. ORION 2.0: A Fast and Accurate NoC Power and Area Model for Early-stage Design Space Exploration. In Design, Automation, and Test in Europe, pages 423-428, April 2009.
14. P. Kermani and L. Kleinrock. Virtual Cut-through: a New Computer Communication Switching Technique. Computer Networks, 3:267-286, September 1979.
15. J. Kim. Low-cost Router Microarchitecture for On-chip Networks. In International Symposium on Microarchitecture, pages 255-266, December 2009.
16. J. Kim, J. Balfour, and W. Dally. Flattened Butterfly Topology for On-chip Networks. In International Symposium on Microarchitecture, pages 172-182, December 2007.
17. A. K. Kodi, A. Sarathy, and A. Louri. iDEAL: Inter-router Dual-Function Energy and Area-Efficient Links for Network-on-Chip (NoC) Architectures. In International Symposium on Computer Architecture, pages 241-250, June 2008.
18. A. Kumar, L.-S. Peh, P. Kundu, and N. K. Jha. Express Virtual Channels: Towards the Ideal Interconnection Fabric. In International Symposium on Computer Architecture, pages 150-161, May 2007.
19. J. W. Lee, M. C. Ng, and K. Asanović. Globally-Synchronized Frames for Guaranteed Quality-of-Service in On-Chip Networks. In International Symposium on Computer Architecture, pages 89-100, June 2008.
20. M. R. Marty and M. D. Hill. Virtual Hierarchies to Support Server Consolidation. In International Symposium on Computer Architecture, pages 46-56, June 2007.
21. G. Michelogiannakis, J. Balfour, and W. Dally. Elastic-buffer Flow Control for On-chip Networks. In International Symposium on High-Performance Computer Architecture, pages 151-162, February 2009.
22. T. Moscibroda and O. Mutlu. A Case for Bufferless Routing in On-Chip Networks. In International Symposium on Computer Architecture, pages 196-207, 2009.
23. N. Muralimanohar, R. Balasubramonian, and N. Jouppi. Optimizing NUCA Organizations and Wiring Alternatives for Large Caches with CACTI 6.0. In International Symposium on Microarchitecture, pages 3-14, December 2007.
24. NVIDIA. NVIDIA's Next Generation CUDA Compute Architecture: Fermi. http: //www.nvidia.com/content/PDF/fermifiwhitefipapers/ NVIDIAfiFermifiComputefiArchitecturefiWhitepaper.pdf, 2009.
25. D. Pham et al. Overview of the Architecture, Circuit Design, and Physical Implementation of a First-Generation Cell Processor. IEEE Journal of Solid-State Circuits, 41(1):179-196, January 2006.
26. D. Schinkel, E. Mensink, E. Klumperink, E. van Tuijl, and B. Nauta. Low-Power, High-Speed Transceivers for Network-on-Chip Communication. IEEE Transactions on VLSI Systems, 17(1):12-21, January 2009.
27. J. Shin, K. Tam, D. Huang, B. Petrick, H. Pham, C. Hwang, H. Li, A. Smith, T. Johnson, F. Schumacher, D. Greenhill, A. Leon, and A. Strong. A 40nm 16-core 128-thread CMT SPARC SoC Processor. In International Solid-State Circuits Conference, pages 98-99, February 2010.
28. Tilera TILE-Gx100. http://www.tilera.com/products/TILE-Gx.php.
29. E. Waingold, M. Taylor, D. Srikrishna, V. Sarkar, W. Lee, V. Lee, J. Kim, M. Frank, P. Finch, R. Barua, J. Babb, S. Amarasinghe, and A. Agarwal. Baring It All to Software: RAW Machines. IEEE Computer, 30(9):86-93, September 1997.
30. H. Wang, L.-S. Peh, and S. Malik. Power-driven Design of Router Microarchitectures in On-chip Networks. In International Symposium on Microarchitecture, pages 105-116, December 2003.
31. D. Wentzlaff, P. Griffin, H. Hoffmann, L. Bao, B. Edwards, C. Ramey, M. Mattina, C.-C. Miao, J. F. B. III, and A. Agarwal. On-Chip Interconnection Architecture of the Tile Processor. IEEE Micro, 27(5):15-31, September/October 2007.