Resilient architectures via collaborative design: Maximizing commodity processor performance in the presence of variations

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Volumn 30, Issue 10, 2011, Pages 1429-1445

  Reddi, Vijay Janapa ^a   Brooks, David ^b  

^a The University of Texas at Austin   (United States)

^b HARVARD UNIVERSITY   (United States)

Author keywords

Dynamic variation; error correction; error detection; error recovery; error resiliency; hw sw co design; inductive noise; power supply noise; reliability; resilient design; resilient microprocessor; timing error; variation; voltage droop

Indexed keywords

DYNAMIC VARIATIONS; ERROR RESILIENCY; HW/SW CODESIGN; INDUCTIVE NOISE; POWER-SUPPLY NOISE; RESILIENT DESIGN; RESILIENT MICROPROCESSOR; TIMING ERRORS; VARIATION; VOLTAGE DROOP;

COMPUTER SYSTEM RECOVERY; DESIGN; ERROR CORRECTION; ERROR DETECTION; MICROPROCESSOR CHIPS; RELIABILITY;

COMPUTER ARCHITECTURE;

EID: 80053284892     PISSN: 02780070     EISSN: None     Source Type: Journal    
DOI: 10.1109/TCAD.2011.2163635     Document Type: Article

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