On-chip decoupling capacitor optimization using architecture level prediction

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Volumn 10, Issue 3, 2002, Pages 319-326

  Pant, Mondira Deb ^a,b   Pant, Pankaj ^a,b   Wills, Donald Scott ^a,c  

^a IEEE   (United States)

^b INTEL CORPORATION   (United States)

^c GEORGIA INSTITUTE OF TECHNOLOGY   (United States)

Author keywords

Decoupling capacitors; Ground bounce; Signal integrity

Indexed keywords

DECOUPLING CAPACITORS; GROUND BOUNCE;

ELECTRIC NETWORK SYNTHESIS; ELECTRIC POTENTIAL; ELECTRIC POWER DISTRIBUTION; ELECTRIC POWER SUPPLIES TO APPARATUS; INDUCTANCE; INTEGRATED CIRCUIT LAYOUT; MICROPROCESSOR CHIPS; SWITCHING CIRCUITS;

CAPACITORS;

EID: 0036625321     PISSN: 10638210     EISSN: None     Source Type: Journal    
DOI: 10.1109/TVLSI.2002.1043335     Document Type: Article

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