An event-guided approach to reducing voltage noise in processors

Proceedings -Design, Automation and Test in Europe, DATE

Volumn , Issue , 2009, Pages 160-165

  Gupta, Meeta S ^a   Reddi, Vijay Janapa ^a   Holloway, Glenn ^a   Wei, Gu Yeon ^a   Brooks, David M ^a  

^a HARVARD UNIVERSITY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

BENCHMARKING; NOISE POLLUTION;

ADAPTIVE METHODS; BRANCH MISPREDICTIONS; CHECKPOINT AND ROLLBACK; CLOCK FREQUENCY; MODERN MICROPROCESSOR; OPERATING MARGINS; SUPPLY-VOLTAGE FLUCTUATION; VOLTAGE EMERGENCIES;

CLOCKS;

EID: 70350075847     PISSN: 15301591     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/date.2009.5090651     Document Type: Conference Paper

References (18)

1. H. Akkary, R. Rajwar, and S. Srinivasan. Checkpoint processing and recovery: Towards scalable large instruction window processors. In MICRO-36, 2003.
2. E. Alon and M. Horowitz. Integrated regulation for energy-efficient digital circuits. In CICC, 2007.
3. H. Ando et al. A 1.3 GHz fifth generation SPARC64 microprocessor. IEEE JSSC, 38, 2003.
4. K. Aygun et al. Power delivery for high-performance microprocessors. Intel Technology Journal, 9, Nov. 2005.
5. K. A. Bowman et al. Energy-efficient and metastability-immune timingerror detection and instruction replay-based recovery circuits for dynamic variation tolerance. In ISSCC, 2008.
6. D. Brooks et al. Power-aware microarchitecture: Design and modeling challenges for next-generation microprocessors. In IEEE-MICRO, 2000.
7. D. Brooks, V. Tiwari, and M. Martonosi. Wattch: A framework for architectural-level power analysis and optimizations. In ISCA-27, 2000.
8. E. Grochowski, D. Ayers, and V. Tiwari. Microarchitectural simulation and control of di/dt-induced power supply voltage variation. In HPCA-8, 2002.
9. M. S. Gupta, K. Rangan, M. D. Smith, G.-Y. Wei, and D. M. Brooks. Towards a software approach to mitigate voltage emergencies. In ISLPED, 2007.
10. M. S. Gupta, K. Rangan, M. D. Smith, G.-Y. Wei, and D. M. Brooks. DeCoR: A delayed commit and rollback mechanism for handling inductive noise in processors. In HPCA-14, 2008.
11. N. James et al. Comparison of split-versus connected-core supplies in the POWER6 microprocessor. In ISSCC, 2007.
12. R. Joseph, D. Brooks, and M. Martonosi. Control techniques to eliminate voltage emergencies in high performance processors. In HPCA-9, 2003.
13. N. Kirman, M. Kirman, M. Chaudhuri, and J. Martinez. Checkpointed early load retirement. In HPCA-11, 2005.
14. J. F. Martínez et al. Cherry: Checkpointed early resource recycling in out-of-order microprocessors. In MICRO-35, 2002.
15. M. D. Powell and T. N. Vijaykumar. Pipeline muffling and a priori current ramping: architectural techniques to reduce high-frequency inductive noise. In ISLPED, 2003.
16. M. D. Powell and T. N. Vijaykumar. Exploiting resonant behavior to reduce inductive noise. In ISCA-28, 2004.
17. V. J. Reddi, M. S. Gupta, G. Holloway, G.-Y. Wei, M. D. Smith, and D. Brooks. Voltage emergency prediction: Using signatures to reduce operating margins. In HPCA-15, 2009. (to appear).
18. N. J. Wang and S. J. Patel. ReStore: Symptom-based soft error detection in microprocessors. IEEE Trans. Dependable Secur. Comput., 3(3):188-201, 2006.