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Volumn , Issue , 2007, Pages 123-128

Towards a software approach to mitigate voltage emergencies

Author keywords

Di dt; Dynamic optimization framework; Hardware software codesign; Voltage emergencies

Indexed keywords

DYNAMIC OPTIMIZATION FRAMEWORK; HARDWARE-SOFTWARE CODESIGN; VOLTAGE EMERGENCIES;

EID: 36949010951     PISSN: 15334678     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/1283780.1283808     Document Type: Conference Paper
Times cited : (43)

References (11)
  • 4
    • 1542359145 scopus 로고    scopus 로고
    • Pipeline muffling and a priori current ramping: Architectural techniques to reduce high-frequency inductive noise
    • M. D. Powell and T. N. Vijaykumar, "Pipeline muffling and a priori current ramping: architectural techniques to reduce high-frequency inductive noise," in Int'l Symposium on Low Power Electronics and Design, 2003.
    • (2003) Int'l Symposium on Low Power Electronics and Design
    • Powell, M.D.1    Vijaykumar, T.N.2
  • 5
    • 84932083885 scopus 로고    scopus 로고
    • Eliminating Voltage Emergencies via Microarchitectural Voltage Control Feedback and Dynamic Optimization
    • August
    • K. Hazelwood and D. Brooks, "Eliminating Voltage Emergencies via Microarchitectural Voltage Control Feedback and Dynamic Optimization," in International Symposium on Low-Power Electronics and Design, August 2004.
    • (2004) International Symposium on Low-Power Electronics and Design
    • Hazelwood, K.1    Brooks, D.2
  • 7
    • 13144291598 scopus 로고    scopus 로고
    • Power Analysis and Instruction Scheduling for Reduced di/dt in the Execution Core of High-Performance Microprocessors,
    • Master's thesis, NC State University, USA
    • M. Toburen, "Power Analysis and Instruction Scheduling for Reduced di/dt in the Execution Core of High-Performance Microprocessors," Master's thesis, NC State University, USA, 1999.
    • (1999)
    • Toburen, M.1


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.