Software-assisted hardware reliability: Abstracting circuit-level challenges to the software stack

Proceedings - Design Automation Conference

Volumn , Issue , 2009, Pages 788-793

  Reddi, Vijay Janapa ^a   Gupta, Meeta S ^a   Smith, Michael D ^a   Wei, Gu Yeon ^a   Brooks, David ^a   Campanoni, Simone ^b  

^a HARVARD UNIVERSITY   (United States)

^b POLITECNICO DI MILANO   (Italy)

Author keywords

Hardware software co design; Runtime optimization

Indexed keywords

COLLABORATIVE APPROACH; CONSTRAINED DESIGN; HARDWARE RELIABILITY; INSTRUCTION STREAMS; OPERATING MARGINS; RECOVERY MECHANISMS; RUN-TIME SOFTWARE; RUNTIME OPTIMIZATION; RUNTIMES; SOFTWARE STACKS; SUPPLY VOLTAGES;

COMPUTER AIDED DESIGN; COMPUTER HARDWARE DESCRIPTION LANGUAGES; DIGITAL INTEGRATED CIRCUITS; DISTRIBUTED COMPUTER SYSTEMS;

SOFTWARE RELIABILITY;

EID: 70350704972     PISSN: 0738100X     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

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