Comparison of split- versus connected-core supplies in the POWER6™ microprocessor

Digest of Technical Papers - IEEE International Solid-State Circuits Conference

Volumn , Issue , 2007, Pages 298-300

  James, Norman ^a   Restle, Phillip ^b   Friedrich, Joshua ^a   Huott, Bill ^a   McCredie, Bradley ^a  

^a IBM   (United States)

^b IBM T J WATSON RESEARCH CENTER   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER SIMULATION; MICROPROCESSOR CHIPS; OPTICAL INTERCONNECTS; SILICON ON INSULATOR TECHNOLOGY;

NOISE MEASUREMENTS; ON-CHIP NOISE MEASUREMENTS; POWER GRID DESIGN;

ELECTRIC POWER SUPPLIES TO APPARATUS;

EID: 34548859786     PISSN: 01936530     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISSCC.2007.373412     Document Type: Conference Paper

References (5)

1. J. Friedrich, B. McCredie, N. Jame, et al., "Design of the POWER6™ Microprocessor," ISSCC Dig. Tech. Papers, pp. 96-97, Feb., 2007.
2. E.B. Cohen, N.J. Rohrer, P. Sandon, et al, "A 64B CPU Pair: Dual-and Single-Processor Chips," ISSCC Dig. Tech. Papers, pp. 106-107, Feb. 2006.
3. P. Restle et al., "Timing Uncertainty Measurements on Power 5 Microprocessor," ISSCC Dig. Tech. Papers, pp. 354-355, Feb 2004
4. A. Drake, R. Senger, H. Deogun, et al., "A Distributed Critical Path Timing Monitor for a 65nm Power Microprocessor," ISSCC Dig. Tech. Papers, pp. 398-399, Feb., 2007.
5. M.G.R. Thomson, P.J. Restle, and N.K. James, "A 5 GHz Duty-Cycle Correcting Clock Distribution Network for the POWER6 Microprocessor," ISSCC Dig. Tech. Papers, pp. 384-355, Feb., 2006.