IBM'S S/390 G5 microprocessor design

IEEE Micro

Volumn 19, Issue 2, 1999, Pages 12-22

  Slegel, Timothy J ^a   Averill III, Robert M ^a,b   Check, Mark A ^a,c   Giamei, Bruce C ^a,d   Krumm, Barry W ^a   Krygowski, Christopher A ^a   Li, Wen H ^a   Liptay, John S ^a   MacDougall, John D ^a   McPherson, Thomas J ^a   Navarro, Jennifer A ^a   Schwarz, Eric M ^a   Shum, Kevin ^a   Webb, Charles F ^a  

^a IBM   (United States)

^b IBM's Poughkeepsie Hardware Laboratory   (United States)

^c IEEE

^d Custom Microprocessor Development Group

Author keywords

[No Author keywords available]

Indexed keywords

BUFFER STORAGE; CMOS INTEGRATED CIRCUITS; CODES (SYMBOLS); COMPUTER ARCHITECTURE; COMPUTER SYSTEMS PROGRAMMING; DECODING; DIGITAL ARITHMETIC; FIELD EFFECT TRANSISTORS; INTEGRATED CIRCUIT LAYOUT; MULTICHIP MODULES; RESPONSE TIME (COMPUTER SYSTEMS); VIRTUAL REALITY;

ABSOLUTE ADDRESS HISTORY TABLES (AAHT); ACCESS REGISTER TRANSLATION (ART); COMPLEX INSTRUCTION SET COMPUTING (CISC); MAINFRAME SYSTEMS; TRANSLATION-LOOKASIDE BUFFERS (TLB);

MICROPROCESSOR CHIPS;

EID: 0032667728     PISSN: 02721732     EISSN: None     Source Type: Journal    
DOI: 10.1109/40.755464     Document Type: Article

References (10)

1. Enterprise Systems Architecture/390 Principles of Operation, order number SA22-7201, available through IBM branch offices.
2. G.S. Rao et al., "IBM S/390 Parallel Enterprise Servers G3 and G4," IBM J. Research and Development, Vol. 41, No. 4/5, July/Sept. 1997, pp. 397-403.
3. C.F. Webb and J.S. Liptay, "A High-Frequency Custom CMOS S/390 Microprocessor," IBM J. Research and Development, Vol. 41, No. 4/5, July/Sept. 1997, pp. 463-473.
4. C.F. Webb et al., "A 400 MHz S/390 Microprocessor," IEEE J. Solid-State Circuits, Vol. 32, No. 11, Nov. 1997, pp. 1,665-1,675.
5. T.J. Siegel et al., "IBM S/390 G5 Microprocessor," Hot Chips 10 Conf. Record, Aug. 1998 (copies available from the author).
6. R.M. Averill III et al., "Deep Submicron Design Techniques for the 500 MHz IBM S/390 G5 Custom Microprocessor," Proc. Int'l Conf. Computer Design, IEEE Computer Soc. Press, Los Alamitos, Calif., Oct. 1998.
7. Large Systems Performance Reference, order number SC28-1187, available through IBM branch offices.
8. K. Hua et al., "Early Resolution of Address Translation in Cache Design," Proc. Int'l Conf. Computer Eng., Sept. 1990.
9. E.M. Schwarz, L. Sigal, and T.J. McPherson, "CMOS Floating-Point Unit for the S/390 Parallel Enterprise Server G4," IBM J. Research and Development, Vol. 41, No. 4/5, July/Sept. 1997, pp. 475-488.
10. E.M. Schwarz, R.M. Smith, and C.A. Krygowski, "The S/390 G5 Floating-point Unit Supporting Hex and Binary Architectures," Proc. 14th IEEE Symp. Computer Arithmetic, to be published by IEEE Computer Soc. Press, Los Alamitos, Calif., Apr. 1999.