Voltage smoothing: Characterizing and mitigating voltage noise in production processors via software-guided thread scheduling

Proceedings of the Annual International Symposium on Microarchitecture, MICRO

Volumn , Issue , 2010, Pages 77-88

  Reddi, Vijay Janapa ^a   Kanev, Svilen ^b   Kim, Wonyoung ^b   Campanoni, Simone ^b   Smith, Michael D ^b   Wei, Gu Yeon ^b   Brooks, David ^b  

^a Advanced Micro Devices (AMD) Research Labs   (United States)

^b HARVARD UNIVERSITY   (United States)

Author keywords

DI dt; Error resiliency; Hardware reliability; Hw sw co design; Inductive noise; Thread scheduling; Voltage droop

Indexed keywords

DI/DT; ERROR RESILIENCY; HARDWARE RELIABILITY; HW/SW CO-DESIGN; INDUCTIVE NOISE; THREAD SCHEDULING; VOLTAGE DROOP;

DESIGN; MICROPROCESSOR CHIPS; RECOVERY; SCHEDULING;

PROGRAM PROCESSORS;

EID: 79951694520     PISSN: 10724451     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/MICRO.2010.35     Document Type: Conference Paper

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